| Line 160... |
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* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme
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* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme
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* No hardware support of unaligned accesses - they will trigger an exception
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* No hardware support of unaligned accesses - they will trigger an exception
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* Little-endian byte order
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* Little-endian byte order
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* All reserved or unimplemented instructions will raise an illegal instruction exception
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* All reserved or unimplemented instructions will raise an illegal instruction exception
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* Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)
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* Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)
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* Official [RISC-V open-source architecture ID](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)
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**RV32I base instruction set** (`I` extension):
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**RV32I base instruction set** (`I` extension):
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* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O3`.
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by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O3`.
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|
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Results generated for hardware version: `1.4.4.8`
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Results generated for hardware version: `1.4.4.8`
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|
|
| CPU | Required Clock Cycles | Executed Instructions | Average CPI |
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| CPU | Required Clock Cycles | Executed Instructions | Average CPI |
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|:------------------------|----------------------:|----------------------:|:-----------:|
|
|:--------------------------|----------------------:|----------------------:|:-----------:|
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| `rv32i` | 5 945 938 586 | 1 469 587 406 | **4.05** |
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| `rv32i` | 5 945 938 586 | 1 469 587 406 | **4.05** |
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| `rv32im` | 3 110 282 586 | 602 225 760 | **5.16** |
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| `rv32im` | 3 110 282 586 | 602 225 760 | **5.16** |
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| `rv32imc` | 3 172 969 968 | 615 388 924 | **5.16** |
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| `rv32imc` | 3 172 969 968 | 615 388 924 | **5.16** |
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| `rv32imc` `FAST_MUL_EN` | 2 590 417 968 | 615 388 890 | **4.21** |
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| `rv32imc` + `FAST_MUL_EN` | 2 590 417 968 | 615 388 890 | **4.21** |
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The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic).
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The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic).
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|
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When the `C` extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
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When the `C` extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
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You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in your own project or you
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You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in your own project or you
|
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) (from the project's
|
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) (from the project's
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[`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder) as top entity.
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[`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder) as top entity.
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|
|
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART lines, clock, reset and some GPIO output sginals are
|
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART lines, clock, reset and some GPIO output signals are
|
propagated as actual entity signals. Basically, it is a FPGA "hello world" example:
|
propagated as actual entity signals. Basically, it is a FPGA "hello world" example:
|
|
|
```vhdl
|
```vhdl
|
entity neorv32_test_setup is
|
entity neorv32_test_setup is
|
port (
|
port (
|
