| Line 89... |
Line 89... |
### To-Do / Wish List / [Help Wanted](#Contribute)
|
### To-Do / Wish List / [Help Wanted](#Contribute)
|
|
|
* Use LaTeX for data sheet
|
* Use LaTeX for data sheet
|
* More support for FreeRTOS
|
* More support for FreeRTOS
|
* Further size and performance optimization
|
* Further size and performance optimization
|
* Add a cache for the external memory interface
|
|
* Synthesis results (+ wrappers?) for more/specific platforms
|
* Synthesis results (+ wrappers?) for more/specific platforms
|
* Maybe port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
|
* Maybe port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
|
* Implement further CPU extensions:
|
* Implement further RISC-V (or custom?) CPU extensions (like floating-point operations ('F'))
|
* Bitmanipulation operations (`B`) - when they are *official*
|
|
* Floating-point instructions (`F`)
|
|
* ...
|
|
* ...
|
* ...
|
|
|
|
#### Work-in-progress
|
|
|
|
* A cache for the external memory/bus interface (also providing burst mode?)
|
|
* RISC-V `B` extension ([bitmanipulation](https://github.com/riscv/riscv-bitmanip))
|
|
|
|
|
## Features
|
## Features
|
|
|
The full-blown data sheet of the NEORV32 Processor and CPU is available as pdf file:
|
The full-blown data sheet of the NEORV32 Processor and CPU is available as pdf file:
|
| Line 178... |
Line 178... |
* System instructions: `MRET` `WFI`
|
* System instructions: `MRET` `WFI`
|
* Counter CSRs: `cycle` `cycleh` `instret` `instreth` `time` `timeh` `mcycle` `mcycleh` `minstret` `minstreth`
|
* Counter CSRs: `cycle` `cycleh` `instret` `instreth` `time` `timeh` `mcycle` `mcycleh` `minstret` `minstreth`
|
* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
|
* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
|
* Supported exceptions and interrupts:
|
* Supported exceptions and interrupts:
|
* Misaligned instruction address
|
* Misaligned instruction address
|
* Instruction access fault
|
* Instruction access fault (via unacknowledged bus access after timeout)
|
* Illegal instruction
|
* Illegal instruction
|
* Breakpoint (via `ebreak` instruction)
|
* Breakpoint (via `ebreak` instruction)
|
* Load address misaligned
|
* Load address misaligned
|
* Load access fault
|
* Load access fault (via unacknowledged bus access after timeout)
|
* Store address misaligned
|
* Store address misaligned
|
* Store access fault
|
* Store access fault (via unacknowledged bus access after timeout)
|
* Environment call from M-mode (via `ecall` instruction)
|
* Environment call from M-mode (via `ecall` instruction)
|
* Machine timer interrupt `mti` (via processor's MTIME unit)
|
* Machine timer interrupt `mti` (via processor's MTIME unit)
|
* Machine software interrupt `msi` (via external signal)
|
* Machine software interrupt `msi` (via external signal)
|
* Machine external interrupt `mei` (via external signal)
|
* Machine external interrupt `mei` (via external signal)
|
* Four fast interrupt requests (custom extension)
|
* Four fast interrupt requests (custom extension)
|
| Line 300... |
Line 300... |
~~~
|
~~~
|
**Configuration**
|
**Configuration**
|
Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock
|
Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
Flags: default, see makefile
|
Compiler flags: default, see makefile
|
Peripherals: UART for printing the results
|
Peripherals: UART for printing the results
|
~~~
|
~~~
|
|
|
| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
|
| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
|
|:--------------------------------------------|:---------------:|:------------:|:--------------:|:-------------:|
|
|:--------------------------------------------|:---------------:|:------------:|:--------------:|:-------------:|
|
