| Line 29... |
Line 29... |
`M`, `C` and `Zicsr` extensions. The CPU was built from scratch and is compliant to the **Unprivileged
|
`M`, `C` and `Zicsr` extensions. The CPU was built from scratch and is compliant to the **Unprivileged
|
ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12**. The NEORV32 is intended
|
ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12**. The NEORV32 is intended
|
as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller.
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as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller.
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|
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The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI,
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The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI,
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interrupt controller, timers and embedded memories. External memories peripherals and custom IP can be attached via a
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interrupt controller, timers and embedded memories. External memories, peripherals and custom IP can be attached via a
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Wishbone-based external memory interface. All optional features beyond the base CPU can be enabled configured via VHDL generics.
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Wishbone-based external memory interface. All optional features beyond the base CPU can be enabled configured via VHDL generics.
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|
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This project comes with a complete software ecosystem that features core libraries for high-level usage of the
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This project comes with a complete software ecosystem that features core libraries for high-level usage of the
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provided functions and peripherals, application makefiles and example programs. All software source files
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provided functions and peripherals, application makefiles and example programs. All software source files
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provide a doxygen-based documentary.
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provide a doxygen-based documentary.
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|
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The project is intended to work "out of the box". Just synthesize the test setup from this project, upload
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The project is intended to work "out of the box". Just synthesize the test setup from this project, upload
|
it to your FPGA board of choice and start playing with the NEORV32. If you do not want to [compile the GCC toolchain](https://github.com/riscv/riscv-gnu-toolchain)
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it to your FPGA board of choice and start playing with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain)
|
by yourself, you can also download [pre-compiled toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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by yourself, you can also download [pre-compiled toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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|
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For more information take a look a the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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For more information take a look a the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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|
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| Line 122... |
Line 122... |
* Custom CSRs: `mfeatures` `mclock` `mispacebase` `mdspacebase` `mispacesize` `mdspacesize`
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* Custom CSRs: `mfeatures` `mclock` `mispacebase` `mdspacebase` `mispacesize` `mdspacesize`
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* Supported exceptions and interrupts:
|
* Supported exceptions and interrupts:
|
* Misaligned instruction address
|
* Misaligned instruction address
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* Instruction access fault
|
* Instruction access fault
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* Illegal instruction
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* Illegal instruction
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* Breakpoint
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* Breakpoint (via `ebreak` instruction)
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* Load address misaligned
|
* Load address misaligned
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* Load access fault
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* Load access fault
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* Sore address misaligned
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* Store address misaligned
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* Store access fault
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* Store access fault
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* Environment call from M-mode
|
* Environment call from M-mode (via `ecall` instruction)
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* Machine software instrrupt
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* Machine software instrrupt
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* Machine timer interrupt (from MTIME)
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* Machine timer interrupt (via `MTIME` unit)
|
* Machine external interrupt (via CLIC)
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* Machine external interrupt (via `CLIC` unit)
|
|
|
**General**:
|
**General**:
|
* No hardware support of unaligned accesses (except for instructions in `C` extension that still have to be aligned on 16-bit boundaries)
|
* No hardware support of unaligned accesses (except for instructions in `C` extension that still have to be aligned on 16-bit boundaries)
|
* Multi-cycle in-order instruction execution
|
* Multi-cycle in-order instruction execution
|
|
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| Line 157... |
Line 157... |
|
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## FPGA Implementation Results
|
## FPGA Implementation Results
|
|
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This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
|
This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
|
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
|
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
|
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not other specified, the default configuration
|
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
|
of the processor's generics is assumed. No constraints were used.
|
of the processor's generics is assumed. No constraints were used.
|
|
|
Results generated for hardware version: `0.0.2.3`
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Results generated for hardware version: `0.0.2.3`
|
|
|
### CPU
|
### CPU
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| Line 179... |
Line 179... |
|
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### Peripherals / Others
|
### Peripherals / Others
|
|
|
| Module | Description | LEs | FFs | Memory bits | DSPs |
|
| Module | Description | LEs | FFs | Memory bits | DSPs |
|
|:---------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
|
|:---------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
|
| Boot ROM | Bootloader ROM (4kB) | 3 | 1 | 32 768 | 0 |
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| BOOT ROM | Bootloader ROM (4kB) | 3 | 1 | 32 768 | 0 |
|
| DEVNULL | Dummy device | 2 | 1 | 0 | 0 |
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| DEVNULL | Dummy device | 2 | 1 | 0 | 0 |
|
| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 |
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| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 |
|
| GPIO | General purpose input/output ports | 37 | 33 | 0 | 0 |
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| GPIO | General purpose input/output ports | 37 | 33 | 0 | 0 |
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| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 |
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| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 |
|
| MTIME | Machine system timer | 369 | 168 | 0 | 0 |
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| MTIME | Machine system timer | 369 | 168 | 0 | 0 |
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| Line 197... |
Line 197... |
|
|
### Lattice iCE40 UltraPlus 5k
|
### Lattice iCE40 UltraPlus 5k
|
|
|
The following table shows the hardware utilization for a [iCE40 UP5K](http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus) FPGA.
|
The following table shows the hardware utilization for a [iCE40 UP5K](http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus) FPGA.
|
The setup uses all provided peripherals, all CPU extensions (except for the `E` extension), no external memory interface and internal
|
The setup uses all provided peripherals, all CPU extensions (except for the `E` extension), no external memory interface and internal
|
instruction and data memoryies (each 64kB) based on SPRAM primitives. The FPGA-specific memory components can be found in the
|
instruction and data memories (each 64kB) based on SPRAM primitives. The FPGA-specific memory components can be found in the
|
[`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up) folder.
|
[`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up) folder.
|
|
|
Place & route reports generated with **Lattice Radiant 1.1. Synplify**. The clock frequency is constrained and generated via the
|
Place & route reports generated with **Lattice Radiant 2.1** using Lattice LSE. The clock frequency
|
PLL from the internal HF oscillator running at 12 MHz.
|
is constrained and generated via the PLL from the internal HF oscillator running at 12 MHz.
|
|
|
| CPU Configuration | Slices | LUT | REG | DSPs | SRAM | EBR | f |
|
Results generated for hardware version: `0.0.2.5`
|
|
|
|
| CPU Configuration | Slices | LUT | REG | DSPs | SPRAM | EBR | f |
|
|:--------------------|:----------:|:----------:|:----------:|:------:|:--------:|:--------:|:---------:|
|
|:--------------------|:----------:|:----------:|:----------:|:------:|:--------:|:--------:|:---------:|
|
| `rv32imc` | 2593 (98%) | 5059 (95%) | 1776 (33%) | 0 (0%) | 4 (100%) | 12 (40%) | 20.25 MHz |
|
| `rv32imc` + `Zicsr` | 2405 (91%) | 4642 (87%) | 1810 (34%) | 0 (0%) | 4 (100%) | 12 (40%) | 20.25 MHz |
|
|
|
|
|
## Performance
|
## Performance
|
|
|
### CoreMark Benchmark
|
### CoreMark Benchmark
|
