| Line 42... |
Line 42... |
* `U` - less-privileged *user mode*
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* `U` - less-privileged *user mode*
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* `Zicsr` - control and status register access instructions (+ exception/irq system)
|
* `Zicsr` - control and status register access instructions (+ exception/irq system)
|
* `Zifencei` - instruction stream synchronization
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* `Zifencei` - instruction stream synchronization
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* `PMP` - physical memory protection
|
* `PMP` - physical memory protection
|
* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
|
* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
|
* optional embedded memories (instructions/data/bootloader, RAM/ROM)
|
* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
|
* timers (watch dog, RISC-V-compliant machine timer)
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* timers (watch dog, RISC-V-compliant machine timer)
|
* serial interfaces (SPI, TWI, UART) and general purpose IO
|
* serial interfaces (SPI, TWI, UART) and general purpose IO
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* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
|
* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
|
* [more ...](#NEORV32-Processor-Features)
|
* [more ...](#NEORV32-Processor-Features)
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* Software framework
|
* Software framework
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| Line 91... |
Line 91... |
|
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### To-Do / Wish List / Help Wanted
|
### To-Do / Wish List / Help Wanted
|
|
|
* Use LaTeX for data sheet
|
* Use LaTeX for data sheet
|
* Further size and performance optimization *(work in progress)*
|
* Further size and performance optimization *(work in progress)*
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* A cache for the external memory/bus interface *(work in progress)*
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* Add associativity configuration for instruction cache
|
|
* Add a data cache
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* Burst mode for the external memory/bus interface
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* Burst mode for the external memory/bus interface
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* RISC-V `B` extension ([bitmanipulation](https://github.com/riscv/riscv-bitmanip)) *(shelved)*
|
* RISC-V `B` extension ([bitmanipulation](https://github.com/riscv/riscv-bitmanip)) *(shelved)*
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* Synthesis results (+ wrappers?) for more/specific platforms
|
* Synthesis results (+ wrappers?) for more/specific platforms
|
* More support for FreeRTOS
|
* More support for FreeRTOS
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* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
|
* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
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| Line 118... |
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|
|
|
|
The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
|
The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
|
is highly customizable via the processor's top generics and already provides the following *optional* modules:
|
is highly customizable via the processor's top generics and already provides the following *optional* modules:
|
|
|
* processor-internal data and instruction memories (**DMEM** / **IMEM**)
|
* processor-internal data and instruction memories (**DMEM** / **IMEM**) & cache (**iCACHE**)
|
* internal **Bootloader** with UART console and automatic application boot from SPI flash option
|
* bootloader (**BOOTLDROM**) with UART console and automatic application boot from SPI flash option
|
* machine system timer (**MTIME**), RISC-V-compliant
|
* machine system timer (**MTIME**), RISC-V-compliant
|
* watchdog timer (**WDT**)
|
* watchdog timer (**WDT**)
|
* universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io
|
* universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io
|
* 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
|
* 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
|
* two wire serial interface controller (**TWI**), with optional clock-stretching, compatible to the I²C standard
|
* two wire serial interface controller (**TWI**), with optional clock-stretching, compatible to the I²C standard
|
| Line 186... |
Line 187... |
**Privileged architecture / CSR access** (`Zicsr` extension):
|
**Privileged architecture / CSR access** (`Zicsr` extension):
|
* Privilege levels: `M-mode` (Machine mode)
|
* Privilege levels: `M-mode` (Machine mode)
|
* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
|
* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
|
* System instructions: `MRET` `WFI`
|
* System instructions: `MRET` `WFI`
|
* Pseudo-instructions are not listed
|
* Pseudo-instructions are not listed
|
* Counter CSRs: `cycle` `cycleh` `instret` `instreth` `time` `timeh` `mcycle` `mcycleh` `minstret` `minstreth`
|
* Counter CSRs: `cycle` `cycleh` `instret` `instreth` `time` `timeh` `mcycle` `mcycleh` `minstret` `minstreth` `mcounteren` `mcountinhibit`
|
* Machine CSRs: `mstatus` `mstatush` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
|
* Machine CSRs: `mstatus` `mstatush` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
|
* Supported exceptions and interrupts:
|
* Supported exceptions and interrupts:
|
* Misaligned instruction address
|
* Misaligned instruction address
|
* Instruction access fault (via unacknowledged bus access after timeout)
|
* Instruction access fault (via unacknowledged bus access after timeout)
|
* Illegal instruction
|
* Illegal instruction
|
| Line 208... |
Line 209... |
|
|
**Privileged architecture / User mode** (`U` extension, requires `Zicsr` extension):
|
**Privileged architecture / User mode** (`U` extension, requires `Zicsr` extension):
|
* Privilege levels: `M-mode` (Machine mode) + `U-mode` (User mode)
|
* Privilege levels: `M-mode` (Machine mode) + `U-mode` (User mode)
|
|
|
**Privileged architecture / instruction stream synchronization** (`Zifencei` extension):
|
**Privileged architecture / instruction stream synchronization** (`Zifencei` extension):
|
* System instructions: `FENCE.I`
|
* System instructions: `FENCE.I` (among others, used to clear and reload instruction cache)
|
|
|
**Privileged architecture / Physical memory protection** (`PMP`, requires `Zicsr` extension):
|
**Privileged architecture / Physical memory protection** (`PMP`, requires `Zicsr` extension):
|
* Additional machine CSRs: `pmpcfg0` `pmpcfg1` `pmpaddr0` `pmpaddr1` `pmpaddr2` `pmpaddr3` `pmpaddr4` `pmpaddr5` `pmpaddr6` `pmpaddr7`
|
* Additional machine CSRs: `pmpcfg0` `pmpcfg1` `pmpaddr0` `pmpaddr1` `pmpaddr2` `pmpaddr3` `pmpaddr4` `pmpaddr5` `pmpaddr6` `pmpaddr7`
|
|
|
|
|
| Line 243... |
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing
|
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing
|
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
|
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
|
of the CPU's generics is assumed (for example no PMP). No constraints were used at all. The `u` and `Zifencei` extensions have
|
of the CPU's generics is assumed (for example no PMP). No constraints were used at all. The `u` and `Zifencei` extensions have
|
a negligible impact on the hardware requirements.
|
a negligible impact on the hardware requirements.
|
|
|
Results generated for hardware version [`1.4.9.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.4.9.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
|
|:----------------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
|
|:----------------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
|
| `rv32i` | 1190 | 512 | 2048 | 0 | 120 MHz |
|
| `rv32i` | 1190 | 512 | 2048 | 0 | 120 MHz |
|
| `rv32i` + `u` + `Zicsr` + `Zifencei` | 1927 | 903 | 2048 | 0 | 123 MHz |
|
| `rv32i` + `u` + `Zicsr` + `Zifencei` | 1927 | 903 | 2048 | 0 | 123 MHz |
|
| Line 258... |
Line 259... |
Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max. However, the size of the register file is cut in half.
|
Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max. However, the size of the register file is cut in half.
|
|
|
|
|
### NEORV32 Processor-Internal Peripherals and Memories
|
### NEORV32 Processor-Internal Peripherals and Memories
|
|
|
Results generated for hardware version [`1.4.9.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.4.9.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
| Module | Description | LEs | FFs | Memory bits | DSPs |
|
| Module | Description | LEs | FFs | Memory bits | DSPs |
|
|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
|
|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
|
| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
|
| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
|
| BUSSWITCH | Mux for CPU I & D interfaces | 65 | 8 | 0 | 0 |
|
| BUSSWITCH | Mux for CPU I & D interfaces | 65 | 8 | 0 | 0 |
|
|
| iCACHE | Proc.-int. nstruction cache (default 1x4x54 bytes) | 234 | 156 | 8 192 | 0 |
|
| CFU0 | Custom functions unit 0 | - | - | - | - |
|
| CFU0 | Custom functions unit 0 | - | - | - | - |
|
| CFU1 | Custom functions unit 1 | - | - | - | - |
|
| CFU1 | Custom functions unit 1 | - | - | - | - |
|
| DMEM | Processor-internal data memory (default 8kB) | 6 | 2 | 65 536 | 0 |
|
| DMEM | Processor-internal data memory (default 8kB) | 6 | 2 | 65 536 | 0 |
|
| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0 |
|
| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0 |
|
| IMEM | Processor-internal instruction memory (default 16kb) | 6 | 2 | 131 072 | 0 |
|
| IMEM | Processor-internal instruction memory (default 16kb) | 6 | 2 | 131 072 | 0 |
|
| Line 317... |
Line 319... |
|
|
Results generated for hardware version [`1.4.7.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.4.7.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
~~~
|
~~~
|
**Configuration**
|
**Configuration**
|
Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock
|
Hardware: 32kB IMEM, 16kB DMEM, no caches, 100MHz clock
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
Compiler flags: default, see makefile
|
Compiler flags: default, see makefile
|
Peripherals: UART for printing the results
|
Peripherals: UART for printing the results
|
~~~
|
~~~
|
