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on the RISC-V-compliant NEORV32 CPU. The processor is intended as *ready-to-go* auxiliary processor within a larger SoC
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on the RISC-V-compliant NEORV32 CPU. The processor is intended as *ready-to-go* auxiliary processor within a larger SoC
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designs or as stand-alone custom microcontroller.
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designs or as stand-alone custom microcontroller.
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The project’s change log is available in the [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) file in the root directory of this repository.
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The project’s change log is available in the [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) file in the root directory of this repository.
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To see the changes between releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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To see the changes between releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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The documentation of the software framework is available online on [GitHub-pages](https://stnolting.github.io/neorv32/files.html).
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For more detailed information take a look at the [:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf).
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For more detailed information take a look at the [:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf).
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### Key Features
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### Key Features
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* RISC-V-[compliant](#Status) 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to
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* RISC-V-[compliant](#Status) 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to
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* Subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)
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* Subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)
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* Subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)
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* Subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)
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* Configurable RISC-V CPU extensions
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* Configurable RISC-V-compliant CPU extensions
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* `A` - atomic memory access instructions (optional)
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* `A` - atomic memory access instructions (optional)
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* `B` - Bit manipulation instructions (optional)
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* `B` - Bit manipulation instructions (optional)
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* `C` - compressed instructions (16-bit) (optional)
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* `C` - compressed instructions (16-bit) (optional)
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* `E` - embedded CPU (reduced register file (optional)
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* `E` - embedded CPU (reduced register file (optional)
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* `I` - base integer instruction set (always enabled)
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* `I` - base integer instruction set (always enabled)
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* [more ...](#NEORV32-Processor-Features)
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* [more ...](#NEORV32-Processor-Features)
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* Software framework
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* Software framework
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* core libraries for high-level usage of the provided functions and peripherals
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* core libraries for high-level usage of the provided functions and peripherals
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* application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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* application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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* GCC-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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* GCC-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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* bootloader with UART interface console
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* runtime environment
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* runtime environment
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* several example programs
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* several example programs
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* [doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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* [doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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* [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
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* [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
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* [**Full-blown data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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* [**Full-blown data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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| Project component | CI status |
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| Project component | CI status |
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|:----------------- |:----------|
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|:----------------- |:----------|
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| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) |
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| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) |
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| [SW Framework Documentation (online)](https://stnolting.github.io/neorv32/files.html) | [](https://stnolting.github.io/neorv32/files.html) |
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| [SW Framework Documentation (online)](https://stnolting.github.io/neorv32/files.html) | [](https://stnolting.github.io/neorv32/files.html) |
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| [Pre-built toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://github.com/stnolting/riscv_gcc_prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) |
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| [Pre-built toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://github.com/stnolting/riscv_gcc_prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md) | [](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22RISC-V+Compliance%22) |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md) | [](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22RISC-V+Compliance%22) |
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### To-Do / Wish List / Help Wanted
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### To-Do / Wish List / Help Wanted
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* Use LaTeX for data sheet
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* Use LaTeX for data sheet
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* Further size and performance optimization
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* Further size and performance optimization
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* Add associativity configuration for instruction cache
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* Further expand associativity configuration of instruction cache (4x/8x set-associativity)
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* Add *data* cache
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* Add data cache
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* Burst mode for the external memory/bus interface
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* Burst mode for the external memory/bus interface
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* RISC-V `F` (using `[Zfinx](https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc)`?) CPU extension (single-precision floating point)
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* RISC-V `F` (using [`Zfinx`](https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc)?) CPU extension (single-precision floating point)
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* Add template (HW module + intrinsics skeleton) for custom instructions?
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* Add template (HW module + intrinsics skeleton) for custom instructions?
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* Synthesis results (+ wrappers?) for more/specific platforms
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* Implement further RISC-V (or custom?) CPU extensions
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* More support for FreeRTOS (like *all* traps)
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* More support for FreeRTOS (like *all* traps)
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* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
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* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
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* Implement further RISC-V (or custom?) CPU extensions
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* Maybe port [CircuitPython](https://circuitpython.org/) (just for fun)
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* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))
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* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))
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* Add memory-mapped trigger to testbench to quit simulation (maybe using VHDL2008's `use std.env.finish`?)
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* ...
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* ...
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* [Ideas?](#ContributeFeedbackQuestions)
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* [Ideas?](#ContributeFeedbackQuestions)
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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of the CPU's generics is assumed (e.g. no physical memory protection, no hardware performance monitors).
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of the CPU's generics is assumed (e.g. no physical memory protection, no hardware performance monitors).
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No constraints were used at all. The `u` and `Zifencei` extensions have a negligible impact on the hardware requirements.
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No constraints were used at all. The `u` and `Zifencei` extensions have a negligible impact on the hardware requirements.
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Results generated for hardware version [`1.4.9.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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Results generated for hardware version [`1.5.0.3`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
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| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
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|:-----------------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
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|:-----------------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
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| `rv32i` | 1190 | 512 | 2048 | 0 | 120 MHz |
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| `rv32i` | 1190 | 512 | 1024 | 0 | 120 MHz |
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| `rv32i` + `u` + `Zicsr` + `Zifencei` | 1927 | 903 | 2048 | 0 | 123 MHz |
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| `rv32i` + `u` + `Zicsr` + `Zifencei` | 1927 | 903 | 1024 | 0 | 123 MHz |
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| `rv32im` + `u` + `Zicsr` + `Zifencei` | 2471 | 1148 | 2048 | 0 | 120 MHz |
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| `rv32im` + `u` + `Zicsr` + `Zifencei` | 2471 | 1148 | 1024 | 0 | 120 MHz |
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| `rv32imc` + `u` + `Zicsr` + `Zifencei` | 2716 | 1165 | 2048 | 0 | 120 MHz |
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| `rv32imc` + `u` + `Zicsr` + `Zifencei` | 2716 | 1165 | 1024 | 0 | 120 MHz |
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| `rv32imac` + `u` + `Zicsr` + `Zifencei` | 2736 | 1168 | 2048 | 0 | 120 MHz |
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| `rv32imac` + `u` + `Zicsr` + `Zifencei` | 2736 | 1168 | 1024 | 0 | 120 MHz |
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| `rv32imacb` + `u` + `Zicsr` + `Zifencei` | 3045 | 1260 | 2048 | 0 | 114 MHz |
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| `rv32imacb` + `u` + `Zicsr` + `Zifencei` | 3045 | 1260 | 1024 | 0 | 114 MHz |
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Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max. However, the size of the register file is cut in half.
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Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max. However, the size of the register file is cut in half.
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### NEORV32 Processor-Internal Peripherals and Memories
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### NEORV32 Processor-Internal Peripherals and Memories
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Results generated for hardware version [`1.4.9.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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Results generated for hardware version [`1.5.0.3`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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| Module | Description | LEs | FFs | Memory bits | DSPs |
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| Module | Description | LEs | FFs | Memory bits | DSPs |
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|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
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|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
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| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
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| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
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| BUSSWITCH | Mux for CPU I & D interfaces | 65 | 8 | 0 | 0 |
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| BUSSWITCH | Mux for CPU I & D interfaces | 65 | 8 | 0 | 0 |
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| iCACHE | Proc.-int. nstruction cache (default 1x4x54 bytes) | 234 | 156 | 8 192 | 0 |
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| i-CACHE | Proc.-int. nstruction cache (default 1x4x64 bytes) | 234 | 156 | 8 192 | 0 |
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| CFU0 | Custom functions unit 0 | - | - | - | - |
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| CFU0 | Custom functions unit 0 | - | - | - | - |
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| CFU1 | Custom functions unit 1 | - | - | - | - |
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| CFU1 | Custom functions unit 1 | - | - | - | - |
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| DMEM | Processor-internal data memory (default 8kB) | 6 | 2 | 65 536 | 0 |
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| DMEM | Processor-internal data memory (default 8kB) | 6 | 2 | 65 536 | 0 |
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| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0 |
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| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0 |
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| IMEM | Processor-internal instruction memory (default 16kb) | 6 | 2 | 131 072 | 0 |
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| IMEM | Processor-internal instruction memory (default 16kb) | 6 | 2 | 131 072 | 0 |
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[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
|
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
|
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
|
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
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|
~~~
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~~~
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**Configuration**
|
**Configuration**
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Hardware: 32kB IMEM, 16kB DMEM, no caches(!), 100MHz clock
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Hardware: 32kB IMEM, 16kB DMEM, no caches, 100MHz clock
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CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
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CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
Compiler flags: default, see makefile
|
Compiler flags: default, see makefile
|
Peripherals: UART for printing the results
|
Peripherals: UART for printing the results
|
~~~
|
~~~
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### Toolchain
|
### Toolchain
|
|
|
At first you need the **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
|
At first you need the **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
|
and build the toolchain by yourself, or you can download a prebuilt one and install it.
|
and build the toolchain by yourself, or you can download a prebuilt one and install it.
|
|
|
:warning: Keep in mind that – for instance – a `rv32imc` toolchain only provides library code compiled with compressed and
|
|
`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
|
|
|
|
To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain).
|
To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain).
|
Make sure to use the `ilp32` or `ilp32e` ABI.
|
Make sure to use the `ilp32` or `ilp32e` ABI.
|
|
|
**Alternatively**, you can download a prebuilt toolchain. I have uploaded the toolchains I am using to GitHub. These toolchains
|
**Alternatively**, you can download a prebuilt toolchain. I have uploaded the toolchains I am using to GitHub. These toolchains
|
were compiled on a 64-bit x86 Ubuntu 20.04 LTS (Ubuntu on Windows, actually). Download the toolchain of choice:
|
were compiled on a 64-bit x86 Ubuntu 20.04 LTS (Ubuntu on Windows, actually). Download the toolchain of choice:
|
[:octocat: github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
|
[:octocat: github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
|
|
|
|
You can also use the toolchains provided by [SiFive](https://github.com/sifive/freedom-tools/releases). These are 64-bit toolchains that can also emit 32-bit
|
|
RISC-V code. They were compiled for more sophisticated machines (`imac`) so the according hardware extensions are *mandatory*
|
|
|
|
:warning: Keep in mind that – for instance – a `rv32imc` toolchain only provides library code compiled with compressed and
|
|
`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
|
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### Dowload the NEORV32 Project
|
### Dowload the NEORV32 Project
|
|
|
Get the sources of the NEORV32 Processor project. The simplest way is using `git clone` (suggested for easy project updates via `git pull`):
|
Get the sources of the NEORV32 Processor project. The simplest way is using `git clone` (suggested for easy project updates via `git pull`):
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#### Proprietary Notice
|
#### Proprietary Notice
|
|
|
"Artix" and "Vivado" are trademarks of Xilinx Inc.
|
"Artix" and "Vivado" are trademarks of Xilinx Inc.
|
|
|
"Cyclone", "Quartus Prime Lite" and "Avalon Bus" are trademarks of Intel Corporation.
|
"Cyclone" and "Quartus Prime Lite" are trademarks of Intel Corporation.
|
|
|
"iCE40", "UltraPlus" and "Radiant" are trademarks of Lattice Semiconductor Corporation.
|
"iCE40", "UltraPlus" and "Radiant" are trademarks of Lattice Semiconductor Corporation.
|
|
|
"AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
|
"AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
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| Line 667... |
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[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!
|
[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!
|
|
|
Continous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).
|
Continous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).
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This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
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This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
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--------
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--------
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