OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [README.md] - Diff between revs 48 and 49

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 48 Rev 49
Line 34... Line 34... 
 
 
 
 
 
 
 
 
### Key Features
 
### Key Features
 
 
 
 
 
* RISC-V 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to
 
* RISC-V 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to
 
  * Subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)
 
  * subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)
 
  * Subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)
 
  * subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)
 
  * Passes the [offcial RISC-V compliance tests](#Status)
 
  * the [offcial RISC-V compliance tests](#Status) (*passing*)
 
* Configurable RISC-V-compliant CPU extensions
 
* Configurable RISC-V-compliant CPU extensions
 
  * [`A`](#Atomic-memory-access-a-extension) - atomic memory access instructions (optional)
 
  * [`A`](#Atomic-memory-access-a-extension) - atomic memory access instructions (optional)
 
  * [`B`](#Bit-manipulation-instructions-B-extension) - Bit manipulation instructions (optional)
 
  * [`B`](#Bit-manipulation-instructions-B-extension) - Bit manipulation instructions (optional)
 
  * [`C`](#Compressed-instructions-C-extension) - compressed instructions (16-bit) (optional)
 
  * [`C`](#Compressed-instructions-C-extension) - compressed instructions (16-bit) (optional)
 
  * [`E`](#Embedded-CPU-version-E-extension) - embedded CPU (reduced register file size) (optional)
 
  * [`E`](#Embedded-CPU-version-E-extension) - embedded CPU (reduced register file size) (optional)
Line 65... Line 65... 
  * application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
 
  * application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
 
  * GCC-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
 
  * GCC-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
 
  * bootloader with UART interface console
 
  * bootloader with UART interface console
 
  * runtime environment
 
  * runtime environment
 
  * several example programs
 
  * several example programs
 
  * [doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
 
  * [doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) software documentation: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
 
  * [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
 
  * [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
 
* [**Full-blown data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
 
* [**Full-blown data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
 
* Completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
 
* Completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
 
* Fully synchronous design, no latches, no gated clocks
 
* Fully synchronous design, no latches, no gated clocks
 
* Small hardware footprint and high operating frequency
 
* Small hardware footprint and high operating frequency
Line 96... Line 96... 
[`riscv-compliance/README.md`](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md).
 
[`riscv-compliance/README.md`](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md).
 
 
 
 
 
| Project component | CI status |
 
| Project component | CI status |
 
|:----------------- |:----------|
 
|:----------------- |:----------|
 
| [NEORV32 processor](https://github.com/stnolting/neorv32)                                             | [![Processor Check](https://github.com/stnolting/neorv32/workflows/Processor%20Check/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) |
 
| [NEORV32 processor](https://github.com/stnolting/neorv32)                                             | [![Processor Check](https://github.com/stnolting/neorv32/workflows/Processor%20Check/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) |
 
| [SW Framework Documentation (online)](https://stnolting.github.io/neorv32/files.html)                 | [![Doc@GitHub-pages](https://github.com/stnolting/neorv32/workflows/Deploy%20SW%20Framework%20Documentation%20to%20GitHub-Pages/badge.svg)](https://stnolting.github.io/neorv32/files.html) |
 
| [SW Framework Documentation (online @GH-pages)](https://stnolting.github.io/neorv32/files.html)       | [![Doc@GitHub-pages](https://github.com/stnolting/neorv32/workflows/Deploy%20SW%20Framework%20Documentation%20to%20GitHub-Pages/badge.svg)](https://stnolting.github.io/neorv32/files.html) |
 
| [Pre-built toolchains](https://github.com/stnolting/riscv-gcc-prebuilt)                               | [![Test Toolchains](https://github.com/stnolting/riscv-gcc-prebuilt/workflows/Test%20Toolchains/badge.svg)](https://github.com/stnolting/riscv-gcc-prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) |
 
| [Pre-built toolchains](https://github.com/stnolting/riscv-gcc-prebuilt)                               | [![Test Toolchains](https://github.com/stnolting/riscv-gcc-prebuilt/workflows/Test%20Toolchains/badge.svg)](https://github.com/stnolting/riscv-gcc-prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) |
 
| [RISC-V compliance test](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md) | [![RISC-V Compliance](https://github.com/stnolting/neorv32/workflows/RISC-V%20Compliance/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22RISC-V+Compliance%22) |
 
| [RISC-V compliance test](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md) | [![RISC-V Compliance](https://github.com/stnolting/neorv32/workflows/RISC-V%20Compliance/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22RISC-V+Compliance%22) |
 
 
 
 
 
 
 
 
 
 
 
 
Line 110... Line 110... 
* Further size and performance optimization
 
* Further size and performance optimization
 
* Further expand associativity configuration of instruction cache (4x/8x set-associativity)?
 
* Further expand associativity configuration of instruction cache (4x/8x set-associativity)?
 
* Add data cache?
 
* Add data cache?
 
* Burst mode for the external memory/bus interface?
 
* Burst mode for the external memory/bus interface?
 
* RISC-V `F` (using [`Zfinx`](https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc)?) CPU extension (single-precision floating point)
 
* RISC-V `F` (using [`Zfinx`](https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc)?) CPU extension (single-precision floating point)
 
* Add template (HW module + intrinsics skeleton) for custom instructions?
 
* Add template (HW module + SW intrinsics skeleton) for custom instructions?
 
* Implement further RISC-V (or custom) CPU extensions?
 
* Implement further RISC-V CPU extensions?
 
* More support for FreeRTOS (like *all* traps)?
 
* More support for FreeRTOS (like *all* traps)?
 
* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))?
 
* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))?
 
* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))?
 
* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))?
 
* Add encryption/decryption/hash accelerator (maybe [XTEA](https://en.wikipedia.org/wiki/XTEA))?
 
* Add encryption/decryption/hash accelerator (maybe [XTEA](https://en.wikipedia.org/wiki/XTEA))?
 
* ...
 
* ...
Line 147... Line 147... 
* 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode
 
* 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode
 
* wrapper for **AXI4-Lite Master Interface** (see [AXI Connectivity](#AXI4-Connectivity))
 
* wrapper for **AXI4-Lite Master Interface** (see [AXI Connectivity](#AXI4-Connectivity))
 
* PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
 
* PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
 
* ring-oscillator-based true random number generator (**TRNG**)
 
* ring-oscillator-based true random number generator (**TRNG**)
 
* custom functions subsystem (**CFS**) for tightly-coupled custom co-processor extensions
 
* custom functions subsystem (**CFS**) for tightly-coupled custom co-processor extensions
 
 
 
* numerically-controlled oscillator (**NCO**) with three independent channels
 
* system configuration information memory to check hardware configuration by software (**SYSINFO**, mandatory - not *optional*)
 
* system configuration information memory to check hardware configuration by software (**SYSINFO**, mandatory - not *optional*)
 
 
 
 
 
 
 
 
 
### NEORV32 CPU Features
 
### NEORV32 CPU Features
 
 
 
 
Line 295... Line 296... 
 
 
 
 
This chapter shows exemplary implementation results of the NEORV32 CPU for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
 
This chapter shows exemplary implementation results of the NEORV32 CPU for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
 
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing
 
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing
 
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
 
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
 
of the CPU's generics is assumed (e.g. no physical memory protection, no hardware performance monitors).
 
of the CPU's generics is assumed (e.g. no physical memory protection, no hardware performance monitors).
 
No constraints were used at all. The `u` and `Zifencei` extensions have a negligible impact on the hardware requirements.
 
No constraints were used at all.
 
 
 
 
 
Results generated for hardware version [`1.5.0.3`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
 
Results generated for hardware version [`1.5.1.4`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
 
 
 
 
 
| CPU Configuration                        | LEs        | FFs      | Memory bits | DSPs | f_max   |
 
| CPU Configuration                        | LEs        | FFs      | Memory bits | DSPs | f_max   |
 
|:-----------------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
 
|:-----------------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
 
| `rv32i`                                  |       1190 |      512 |        1024 |    0 | 120 MHz |
 
| `rv32i`                                  |        979 |      409 |        1024 |    0 | 123 MHz |
 
| `rv32i`     + `u` + `Zicsr` + `Zifencei` |       1927 |      903 |        1024 |    0 | 123 MHz |
 
| `rv32i`     + `Zicsr`                    |       1789 |      847 |        1024 |    0 | 122 MHz |
 
| `rv32im`    + `u` + `Zicsr` + `Zifencei` |       2471 |     1148 |        1024 |    0 | 120 MHz |
 
| `rv32im`    + `Zicsr`                    |       2381 |     1125 |        1024 |    0 | 122 MHz |
 
| `rv32imc`   + `u` + `Zicsr` + `Zifencei` |       2716 |     1165 |        1024 |    0 | 120 MHz |
 
| `rv32imc`   + `Zicsr`                    |       2608 |     1140 |        1024 |    0 | 122 MHz |
 
| `rv32imac`  + `u` + `Zicsr` + `Zifencei` |       2736 |     1168 |        1024 |    0 | 120 MHz |
 
| `rv32imac`  + `Zicsr`                    |       2621 |     1144 |        1024 |    0 | 122 MHz |
 
| `rv32imacb` + `u` + `Zicsr` + `Zifencei` |       3045 |     1260 |        1024 |    0 | 116 MHz |
 
| `rv32imacb` + `Zicsr`                    |       3013 |     1310 |        1024 |    0 | 122 MHz |
 
 
 
| `rv32imacb` + `Zicsr` + `u`              |       3031 |     1313 |        1024 |    0 | 122 MHz |
 
 
 
| `rv32imacb` + `Zicsr` + `u` + `Zifencei` |       3050 |     1313 |        1024 |    0 | 116 MHz |
 
 
 
 
 
Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max. However, the size of the register file is cut in half.
 
Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max as the according `I` configuration.
 
 
 
However, the size of the register file is cut in half.
 
 
 
 
 
 
 
 
 
### NEORV32 Processor-Internal Peripherals and Memories
 
### NEORV32 Processor-Internal Peripherals and Memories
 
 
 
 
 
Results generated for hardware version [`1.5.0.3`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
 
Results generated for hardware version [`1.5.1.4`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
 
 
 
 
 
| Module    | Description                                          | LEs | FFs | Memory bits | DSPs |
 
| Module    | Description                                          | LEs | FFs | Memory bits | DSPs |
 
|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
 
|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
 
| BOOT ROM  | Bootloader ROM (default 4kB)                         |   3 |   1 |      32 768 |    0 |
 
| BOOT ROM  | Bootloader ROM (default 4kB)                         |   3 |   1 |      32 768 |    0 |
 
| BUSSWITCH | Mux for CPU I & D interfaces                         |  65 |   8 |           0 |    0 |
 
| BUSSWITCH | Bus mux for CPU instr. & data interfaces             |  65 |   8 |           0 |    0 |
 
| i-CACHE   | Proc.-int. nstruction cache (default 1x4x64 bytes)   | 234 | 156 |       8 192 |    0 |
 
| i-CACHE   | Proc.-int. nstruction cache (default 1x4x64 bytes)   | 234 | 156 |       8 192 |    0 |
 
| CFS       | Custom functions subsystem                           |   - |   - |           - |    - |
 
| CFS       | Custom functions subsystem                           |   - |   - |           - |    - |
 
| DMEM      | Processor-internal data memory (default 8kB)         |   6 |   2 |      65 536 |    0 |
 
| DMEM      | Processor-internal data memory (default 8kB)         |   6 |   2 |      65 536 |    0 |
 
| GPIO      | General purpose input/output ports                   |  67 |  65 |           0 |    0 |
 
| GPIO      | General purpose input/output ports                   |  67 |  65 |           0 |    0 |
 
| IMEM      | Processor-internal instruction memory (default 16kb) |   6 |   2 |     131 072 |    0 |
 
| IMEM      | Processor-internal instruction memory (default 16kb) |   6 |   2 |     131 072 |    0 |
 
| MTIME     | Machine system timer                                 | 274 | 166 |           0 |    0 |
 
| MTIME     | Machine system timer                                 | 274 | 166 |           0 |    0 |
 
 
 
| NCO       | Numerically-controlled oscillator                    | 254 | 226 |           0 |    0 |
 
| PWM       | Pulse-width modulation controller                    |  71 |  69 |           0 |    0 |
 
| PWM       | Pulse-width modulation controller                    |  71 |  69 |           0 |    0 |
 
| SPI       | Serial peripheral interface                          | 138 | 124 |           0 |    0 |
 
| SPI       | Serial peripheral interface                          | 138 | 124 |           0 |    0 |
 
| SYSINFO   | System configuration information memory              |  11 |  10 |           0 |    0 |
 
| SYSINFO   | System configuration information memory              |  11 |  10 |           0 |    0 |
 
| TRNG      | True random number generator                         | 132 | 105 |           0 |    0 |
 
| TRNG      | True random number generator                         | 132 | 105 |           0 |    0 |
 
| TWI       | Two-wire interface                                   |  77 |  46 |           0 |    0 |
 
| TWI       | Two-wire interface                                   |  77 |  46 |           0 |    0 |

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.