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[](https://github.com/stnolting/neorv32)
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[](https://github.com/stnolting/neorv32)
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# The NEORV32 RISC-V Processor
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# The NEORV32 RISC-V Processor
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22RISC-V+Compliance%22)
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[](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/releases)
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* [Overview](#Overview)
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* [Overview](#Overview)
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* [Status](#Status)
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* [Status](#Status)
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## Overview
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## Overview
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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on the RISC-V-compliant NEORV32 CPU. The processor is intended as *ready-to-go* auxiliary processor within a larger SoC
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on the RISC-V NEORV32 CPU. The processor is intended as *ready-to-go* auxiliary processor within a larger SoC
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designs or as stand-alone custom microcontroller.
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designs or as stand-alone custom microcontroller.
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:books: For detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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:books: For detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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The doxygen-based documentation of the *software framework* is available online at [GitHub-pages](https://stnolting.github.io/neorv32/files.html).
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The doxygen-based documentation of the *software framework* is available online at [GitHub-pages](https://stnolting.github.io/neorv32/files.html).
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:label: The project’s change log is available as [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) in the root directory of this repository.
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:label: The project’s change log is available as [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) in the root directory of this repository.
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To see the changes between *stable* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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To see the changes between *stable* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current ideas, ToDos, features being planned and work being in-progress.
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:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
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**TODOs**, features being **planned** and **work-in-progress**.
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:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a [new discussion](https://github.com/stnolting/neorv32/discussions)
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:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a [new discussion](https://github.com/stnolting/neorv32/discussions)
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if you have questions, comments, ideas or bug-fixes. Check out how to [contribute](#ContributeFeedbackQuestions).
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if you have questions, comments, ideas or bug-fixes. Check out how to [contribute](#ContributeFeedbackQuestions).
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### Key Features
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### Key Features
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* RISC-V 32-bit `rv32` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to
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* RISC-V 32-bit `rv32` [**NEORV32 CPU**](#NEORV32-CPU-Features), compatible to
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* subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)
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* subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)
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* subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)
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* subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)
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* the [official RISC-V compliance tests](#Status) (*passing*)
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* the [official RISC-V architecture tests](#Status) (*passing*)
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* Configurable RISC-V-compliant CPU extensions
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* Configurable RISC-V-compatible CPU extensions
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* [`A`](#A---Atomic-memory-access-extension) - atomic memory access instructions (optional)
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* [`A`](#A---Atomic-memory-access-extension) - atomic memory access instructions (optional)
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* [`B`](#B---Bit-manipulation-instructions-extension) - Bit manipulation instructions (optional)
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* [`B`](#B---Bit-manipulation-instructions-extension) - Bit manipulation instructions (optional) :construction:
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* [`C`](#C---Compressed-instructions-extension) - compressed instructions (16-bit) (optional)
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* [`C`](#C---Compressed-instructions-extension) - compressed instructions (16-bit) (optional)
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* [`E`](#E---Embedded-CPU-version-extension) - embedded CPU (reduced register file size) (optional)
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* [`E`](#E---Embedded-CPU-version-extension) - embedded CPU (reduced register file size) (optional)
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* [`I`](#I---Base-integer-instruction-set) - base integer instruction set (always enabled)
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* [`I`](#I---Base-integer-instruction-set) - base integer instruction set (always enabled)
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* [`M`](#M---Integer-multiplication-and-division-hardware-extension) - integer multiplication and division hardware (optional)
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* [`M`](#M---Integer-multiplication-and-division-hardware-extension) - integer multiplication and division hardware (optional)
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* [`U`](#U---Privileged-architecture---User-mode-extension) - less-privileged *user mode* (optional)
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* [`U`](#U---Privileged-architecture---User-mode-extension) - less-privileged *user mode* (optional)
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* [`Zifencei`](#Zifencei---Privileged-architecture---Instruction-stream-synchronization-extension) - instruction stream synchronization (optional)
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* [`Zifencei`](#Zifencei---Privileged-architecture---Instruction-stream-synchronization-extension) - instruction stream synchronization (optional)
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* [`PMP`](#PMP---Privileged-architecture---Physical-memory-protection) - physical memory protection (optional)
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* [`PMP`](#PMP---Privileged-architecture---Physical-memory-protection) - physical memory protection (optional)
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* [`HPM`](#HPM---Privileged-architecture---Hardware-performance-monitors) - hardware performance monitors (optional)
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* [`HPM`](#HPM---Privileged-architecture---Hardware-performance-monitors) - hardware performance monitors (optional)
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* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
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* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
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* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
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* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
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* timers (watch dog, RISC-V-compliant machine timer)
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* timers (watch dog, RISC-V-compatible machine timer)
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* serial interfaces (SPI, TWI, UARTs)
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* serial interfaces (SPI, TWI, UARTs)
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* general purpose IO and PWM channels
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* general purpose IO and PWM channels
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* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
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* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
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* dedicated NeoPixel(c) LED interface
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* subsystem for custom co-processors
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* subsystem for custom co-processors
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* [more ...](#NEORV32-Processor-Features)
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* [more ...](#NEORV32-Processor-Features)
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* Software framework
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* Software framework
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* core libraries for high-level usage of the provided functions and peripherals
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* core libraries for high-level usage of the provided functions and peripherals
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* application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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* application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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### Status
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### Status
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The processor is [synthesizable](#FPGA-Implementation-Results) (tested on *real hardware* using Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/Synplify Pro) and can successfully execute
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The processor is [synthesizable](#FPGA-Implementation-Results) (tested on *real hardware* using Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/Synplify Pro) and can successfully execute
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark).
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark).
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**RISC-V Compliance**: The processor passes the official `rv32_m/C`, `rv32_m/I`, `rv32_m/M`, `rv32_m/privilege` and `rv32_m/Zifencei`
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**RISC-V Architecture Tests**: The processor passes the official `rv32_m/C`, `rv32_m/I`, `rv32_m/M`, `rv32_m/privilege` and `rv32_m/Zifencei`
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[RISC-V compliance](https://github.com/riscv/riscv-compliance) tests. More information regarding the NEORV32 port of the compliance framework can be found in
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[riscv-arch-test](https://github.com/riscv/riscv-arch-test) tests. More information regarding the NEORV32 port of the riscv-arch-test test framework can be found in
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[`riscv-compliance/README.md`](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md).
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[`riscv-arch-test/README.md`](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md).
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| Project component | CI status |
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| Project component | CI status |
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|:----------------- |:----------|
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|:----------------- |:----------|
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| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) |
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| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) |
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| [SW Framework Documentation (online @GH-pages)](https://stnolting.github.io/neorv32/files.html) | [](https://stnolting.github.io/neorv32/files.html) |
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| [SW Framework Documentation (online at GH-pages)](https://stnolting.github.io/neorv32/files.html) | [](https://stnolting.github.io/neorv32/files.html) |
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| [Pre-built toolchains](https://github.com/stnolting/riscv-gcc-prebuilt) | [](https://github.com/stnolting/riscv-gcc-prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) |
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| [Pre-built toolchains](https://github.com/stnolting/riscv-gcc-prebuilt) | [](https://github.com/stnolting/riscv-gcc-prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md) | [](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22RISC-V+Compliance%22) |
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| [RISC-V architecture test](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md) | [](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml) |
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## Features
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## Features
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The full-blown data sheet of the NEORV32 Processor and CPU is available as pdf file:
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The full-blown data sheet of the NEORV32 Processor and CPU is available as pdf file:
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The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
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The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
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is highly customizable via the processor's top generics and already provides the following *optional* modules:
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is highly customizable via the processor's top generics and already provides the following *optional* modules:
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* processor-internal data and instruction memories (**DMEM** / **IMEM**) & cache (**iCACHE**)
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* processor-internal data and instruction memories (**DMEM** / **IMEM**) & cache (**iCACHE**)
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* bootloader (**BOOTLDROM**) with UART console and automatic application boot from SPI flash option
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* bootloader (**BOOTLDROM**) with UART console and automatic application boot from SPI flash option
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* machine system timer (**MTIME**), RISC-V-compliant
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* machine system timer (**MTIME**), RISC-V-compatible
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* watchdog timer (**WDT**)
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* watchdog timer (**WDT**)
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* two independent universal asynchronous receivers and transmitters (**UART0** & **UART1**) with optional hardware flow control (RTS/CTS)
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* two independent universal asynchronous receivers and transmitters (**UART0** & **UART1**) with optional hardware flow control (RTS/CTS)
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* 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
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* 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
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* two wire serial interface controller (**TWI**), with optional clock-stretching, compatible to the I²C standard
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* two wire serial interface controller (**TWI**), with optional clock-stretching, compatible to the I²C standard
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* general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
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* general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
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* 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**)
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* 32-bit external bus interface, Wishbone b4 compatible (**WISHBONE**)
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* wrapper for **AXI4-Lite Master Interface** (see [AXI Connectivity](#AXI4-Connectivity))
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* wrapper for **AXI4-Lite Master Interface** (see [AXI Connectivity](#AXI4-Connectivity))
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* PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
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* PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
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* ring-oscillator-based true random number generator (**TRNG**)
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* ring-oscillator-based true random number generator (**TRNG**)
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* custom functions subsystem (**CFS**) for tightly-coupled custom co-processor extensions
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* custom functions subsystem (**CFS**) for tightly-coupled custom co-processor extensions
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* numerically-controlled oscillator (**NCO**) with three independent channels
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* numerically-controlled oscillator (**NCO**) with three independent channels
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* smart LED interface (**NEOLED**) - WS2812 / NeoPixel(c) compatible
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* system configuration information memory to check hardware configuration by software (**SYSINFO**)
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* system configuration information memory to check hardware configuration by software (**SYSINFO**)
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### NEORV32 CPU Features
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### NEORV32 CPU Features
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The NEORV32 CPU is **compliant** to the
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The NEORV32 CPU implements the
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[official RISC-V specifications (2.2)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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[official RISC-V specifications (2.2)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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[RISC-V privileged architecture specifications (1.12-draft)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf)
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[RISC-V privileged architecture specifications (1.12-draft)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf)
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tested via the [official RISC-V Compliance Test Framework](https://github.com/riscv/riscv-compliance)
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- tested via the [official riscv-arch-test Test Framework](https://github.com/riscv/riscv-arch-test)
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(see [`riscv-compliance/README`](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md)).
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(see [`riscv-arch-test/README`](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md)).
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More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in
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More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in
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the [:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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the [:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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* Supported instructions: `LR.W` (load-reservate) `SC.W` (store-conditional)
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* Supported instructions: `LR.W` (load-reservate) `SC.W` (store-conditional)
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#### `B` - Bit manipulation instructions extension
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#### `B` - Bit manipulation instructions extension
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* :warning: Extension is not officially ratified yet by the RISC-V foundation!
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* :construction: **WORK-IN-PROGRESS** :construction:
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* Implies `Zbb` & `Zbs` sub-extensions (the remaining `B` sub-extensions are not supported yet)
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* :warning: The bit-manipulation extension has not been officially ratified yet!
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* Compatible to [v0.94-draft](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/bitmanip-draft.pdf) of the bit manipulation spec
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* Compatible to [v0.94-draft](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/bitmanip-draft.pdf) of the bit manipulation spec
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* Support via intrisc library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation))
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* Support via intrisc library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation))
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* `Zbb` Base instruction set: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR[I]` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`)
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* `Zbb` base instruction set: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR[I]` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`)
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* `Zbs` Single-bit instructions: `SBSET[I]` `SBCLR[I]` `SBINV[I]` `SBEXT[I]`
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* `Zbs` single-bit instructions: `SBSET[I]` `SBCLR[I]` `SBINV[I]` `SBEXT[I]`
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#### `C` - Compressed instructions extension
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#### `C` - Compressed instructions extension
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* ALU instructions: `C.ADDI4SPN` `C.ADD[I]` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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* ALU instructions: `C.ADDI4SPN` `C.ADD[I]` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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* System instructions: `C.EBREAK` (only with `Zicsr` extension)
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* System instructions: `C.EBREAK` (requires `Zicsr` extension)
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* Floating-point instructions: `C.FLW` `C.FSW` `C.FLWSP` `C.FSWSP` (requires `F` extension)
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* Pseudo-instructions are not listed
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* Pseudo-instructions are not listed
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#### `E` - Embedded CPU version extension
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#### `E` - Embedded CPU version extension
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* Reduced register file (only the 16 lowest registers)
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* Reduced register file (only the 16 lowest registers are implemented)
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#### `F` - Single-precision floating-point extension
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* :construction: **WORK-IN-PROGRESS** :construction:
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* :warning: the `F` extension is not operational yet!
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* :information_source: check out the [F-extension project board](https://github.com/stnolting/neorv32/projects/4) for the current implementation state
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#### `I` - Base integer instruction set
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#### `I` - Base integer instruction set
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* ALU instructions: `LUI` `AUIPC` `ADD[I]` `SLT[I][U]` `XOR[I]` `OR[I]` `AND[I]` `SLL[I]` `SRL[I]` `SRA[I]` `SUB`
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* ALU instructions: `LUI` `AUIPC` `ADD[I]` `SLT[I][U]` `XOR[I]` `OR[I]` `AND[I]` `SLL[I]` `SRL[I]` `SRA[I]` `SUB`
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* CSR access instructions: `CSRRW[I]` `CSRRS[I]` `CSRRC[I]`
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* CSR access instructions: `CSRRW[I]` `CSRRS[I]` `CSRRC[I]`
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* System instructions: `MRET` `WFI`
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* System instructions: `MRET` `WFI`
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* Pseudo-instructions are not listed
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* Pseudo-instructions are not listed
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* Counter CSRs: `[m]cycle[h]` `[m]instret[m]` `time[h]` `[m]hpmcounter*[h]`(3..31, configurable) `mcounteren` `mcountinhibit` `mhpmevent*`(3..31, configurable)
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* Counter CSRs: `[m]cycle[h]` `[m]instret[m]` `time[h]` `[m]hpmcounter*[h]`(3..31, configurable) `mcounteren` `mcountinhibit` `mhpmevent*`(3..31, configurable)
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* Machine CSRs: `mstatus[h]` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
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* Machine CSRs: `mstatus[h]` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
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* Supported (sync.) exceptions (all RISC-V-compliant):
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* Supported (sync.) exceptions (implementing the RISC-V specs):
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* Misaligned instruction address
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* Misaligned instruction address
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* Instruction access fault (via timeout/error after unacknowledged bus access)
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* Instruction access fault (via timeout/error after unacknowledged bus access)
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* Illegal instruction
|
* Illegal instruction
|
* Breakpoint (via `ebreak` instruction)
|
* Breakpoint (via `ebreak` instruction)
|
* Load address misaligned
|
* Load address misaligned
|
| Line 237... |
Line 248... |
* Store address misaligned
|
* Store address misaligned
|
* Store access fault (via unacknowledged bus access after timeout)
|
* Store access fault (via unacknowledged bus access after timeout)
|
* Environment call from U-mode (via `ecall` instruction in user mode)
|
* Environment call from U-mode (via `ecall` instruction in user mode)
|
* Environment call from M-mode (via `ecall` instruction in machine mode)
|
* Environment call from M-mode (via `ecall` instruction in machine mode)
|
* Supported (async.) exceptions / interrupts:
|
* Supported (async.) exceptions / interrupts:
|
* Machine timer interrupt `mti` (via processor's MTIME unit / external signal), RISC-V-compliant
|
* Machine timer interrupt `mti` (via processor's MTIME unit / external signal)
|
* Machine software interrupt `msi` (via external signal), RISC-V-compliant
|
* Machine software interrupt `msi` (via external signal)
|
* Machine external interrupt `mei` (via external signal), RISC-V-compliant
|
* Machine external interrupt `mei` (via external signal)
|
* 16 fast interrupt requests (custom extension), 6+1 available for custom usage
|
* 16 fast interrupt requests (custom extension), 6+1 available for custom usage
|
|
|
|
|
#### `Zifencei` - Privileged architecture - Instruction stream synchronization extension
|
#### `Zifencei` - Privileged architecture - Instruction stream synchronization extension
|
|
|
| Line 262... |
Line 273... |
* Requires `Zicsr` extension
|
* Requires `Zicsr` extension
|
* Configurable number of counters (0..29)
|
* Configurable number of counters (0..29)
|
* Additional machine CSRs: `mhpmevent*`(3..31) `[m]hpmcounter*[h]`(3..31)
|
* Additional machine CSRs: `mhpmevent*`(3..31) `[m]hpmcounter*[h]`(3..31)
|
|
|
|
|
### :warning: Non-RISC-V-Compliant Issues and Limitations
|
### :warning: Non-RISC-V-Compatible Issues and Limitations
|
|
|
* CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus interface provides big- and little-endian configurations
|
* CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus interface provides big- and little-endian configurations
|
* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
|
* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
|
* The physical memory protection (**PMP**) only supports `NAPOT` mode yet and a minimal granularity of 8 bytes
|
* The physical memory protection (**PMP**) only supports `NAPOT` mode yet and a minimal granularity of 8 bytes
|
* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all further AMO operations
|
* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all further AMO operations
|
* The `mcause` trap code `0x80000000` (originally reserved in the RISC-V specs) is used to indicate a hardware reset (as "non-maskable interrupt")
|
* The `mcause` trap code `0x80000000` (originally reserved in the RISC-V specs) is used to indicate a hardware reset (as "non-maskable interrupt")
|
* The bit manipulation extension is not yet officially ratified, but is expected to stay unchanged. There is no software support in the upstream GCC RISC-V port yet. However, an intrinsic library is provided to utilize the provided bit manipulation extension from C-language code (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation)). NEORV32's `B` extension is compliant to spec. version "0.94-draft".
|
* The bit manipulation extension is not yet officially ratified, but is expected to stay unchanged. There is no software support in the upstream GCC RISC-V port yet. However, an intrinsic library is provided to utilize the provided bit manipulation extension from C-language code (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation)). NEORV32's `B` extension is compatible to spec. version "0.94-draft".
|
|
|
|
|
|
|
## FPGA Implementation Results
|
## FPGA Implementation Results
|
|
|
| Line 302... |
Line 313... |
However, the size of the register file is cut in half.
|
However, the size of the register file is cut in half.
|
|
|
|
|
### NEORV32 Processor-Internal Peripherals and Memories
|
### NEORV32 Processor-Internal Peripherals and Memories
|
|
|
Results generated for hardware version [`1.5.1.4`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.5.2.4`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
| Module | Description | LEs | FFs | Memory bits | DSPs |
|
| Module | Description | LEs | FFs | Memory bits | DSPs |
|
|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
|
|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
|
| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
|
| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
|
| BUSSWITCH | Bus mux for CPU instr. & data interfaces | 65 | 8 | 0 | 0 |
|
| BUSSWITCH | Bus mux for CPU instr. & data interfaces | 65 | 8 | 0 | 0 |
|
| Line 315... |
Line 326... |
| DMEM | Processor-internal data memory (default 8kB) | 6 | 2 | 65 536 | 0 |
|
| DMEM | Processor-internal data memory (default 8kB) | 6 | 2 | 65 536 | 0 |
|
| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0 |
|
| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0 |
|
| IMEM | Processor-internal instruction memory (default 16kb) | 6 | 2 | 131 072 | 0 |
|
| IMEM | Processor-internal instruction memory (default 16kb) | 6 | 2 | 131 072 | 0 |
|
| MTIME | Machine system timer | 274 | 166 | 0 | 0 |
|
| MTIME | Machine system timer | 274 | 166 | 0 | 0 |
|
| NCO | Numerically-controlled oscillator | 254 | 226 | 0 | 0 |
|
| NCO | Numerically-controlled oscillator | 254 | 226 | 0 | 0 |
|
|
| NEOLED | Smart LED Interface (NeoPixel-compatibile) [4x FIFO] | 347 | 309 | 0 | 0 |
|
| PWM | Pulse-width modulation controller | 71 | 69 | 0 | 0 |
|
| PWM | Pulse-width modulation controller | 71 | 69 | 0 | 0 |
|
| SPI | Serial peripheral interface | 138 | 124 | 0 | 0 |
|
| SPI | Serial peripheral interface | 138 | 124 | 0 | 0 |
|
| SYSINFO | System configuration information memory | 11 | 10 | 0 | 0 |
|
| SYSINFO | System configuration information memory | 11 | 10 | 0 | 0 |
|
| TRNG | True random number generator | 132 | 105 | 0 | 0 |
|
| TRNG | True random number generator | 132 | 105 | 0 | 0 |
|
| TWI | Two-wire interface | 77 | 46 | 0 | 0 |
|
| TWI | Two-wire interface | 77 | 46 | 0 | 0 |
|
| Line 667... |
Line 679... |
|
|
"iCE40", "UltraPlus" and "Radiant" are trademarks of Lattice Semiconductor Corporation.
|
"iCE40", "UltraPlus" and "Radiant" are trademarks of Lattice Semiconductor Corporation.
|
|
|
"AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
|
"AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
|
|
|
|
"NeoPixel" is a trademark of Adafruit Industries.
|
|
|
|
|
|
|
## Acknowledgements
|
## Acknowledgements
|
|
|
[](https://riscv.org/)
|
[](https://riscv.org/)
|
