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[](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22)
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[](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml)
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[](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
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* [Overview](#Overview)
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* [Overview](#Overview)
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* [Status](#Status)
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* [Status](#Status)
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* [Features](#Features)
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* [Features](#Features)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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on the RISC-V NEORV32 CPU. The processor is intended as auxiliary processor in larger SoC
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on the RISC-V NEORV32 CPU. The processor is intended as auxiliary processor in larger SoC
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designs or as *ready-to-go* stand-alone custom microcontroller.
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designs or as *ready-to-go* stand-alone custom microcontroller.
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:books: For detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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:books: For detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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The `asciidoc` sources can be found in [`docs/src_adoc`](https://github.com/stnolting/neorv32/blob/master/docs/src_adoc). The latest automatic build
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can be downloaded as artifacts from the [_Build Data Sheet_ GitHub workflow](https://github.com/stnolting/neorv32/actions/workflows/build_datasheet.yml).
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The doxygen-based documentation of the *software framework* is available online at [GitHub-pages](https://stnolting.github.io/neorv32/files.html).
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The doxygen-based documentation of the *software framework* is available online at [GitHub-pages](https://stnolting.github.io/neorv32/files.html).
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:label: The project’s change log is available as [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) in the root directory of this repository.
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:label: The project’s change log is available as [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) in the root directory of this repository.
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To see the changes between *stable* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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To see the changes between *stable* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k low-power FPGA running at 22+ MHz.
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k low-power FPGA running at 22+ MHz.
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### Status
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### Status
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The processor is [synthesizable](#FPGA-Implementation-Results) (tested on *real hardware* using Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/Synplify Pro) and can successfully execute
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The processor is [synthesizable](#FPGA-Implementation-Results) (tested on *real hardware* using Intel Quartus Prime, Xilinx Vivado and Lattice Radiant) and can successfully execute
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark).
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark) and the custom
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NEORV32 processor check ([`sw/example/cpu_test`](https://github.com/stnolting/neorv32/tree/master/sw/example/cpu_test), see the status report in the according
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[GitHub workflow](https://github.com/stnolting/neorv32/actions/workflows/processor-check.yml)).
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**RISC-V Architecture Tests**: The processor passes the official `rv32_m/C`, `rv32_m/I`, `rv32_m/M`, `rv32_m/privilege` and `rv32_m/Zifencei`
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**RISC-V Architecture Tests**: The processor passes the official `rv32_m/C`, `rv32_m/I`, `rv32_m/M`, `rv32_m/privilege` and `rv32_m/Zifencei`
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[riscv-arch-test](https://github.com/riscv/riscv-arch-test) tests. More information regarding the NEORV32 port of the riscv-arch-test test framework can be found in
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[riscv-arch-test](https://github.com/riscv/riscv-arch-test) tests. More information regarding the NEORV32 port of the riscv-arch-test test framework can be found in
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[`riscv-arch-test/README.md`](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md).
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[`riscv-arch-test/README.md`](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md).
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| Project component | CI status |
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| Project component | CI status |
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|:----------------- |:----------|
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|:----------------- |:----------|
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| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) |
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| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) |
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| [SW Framework Documentation (online at GH-pages)](https://stnolting.github.io/neorv32/files.html) | [](https://stnolting.github.io/neorv32/files.html) |
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| [SW Framework Documentation (online at GH-pages)](https://stnolting.github.io/neorv32/files.html) | [](https://stnolting.github.io/neorv32/files.html) |
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| Build data sheet from `asciidoc` sources | [](https://github.com/stnolting/neorv32/actions/workflows/build_datasheet.yml) |
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| [Pre-built toolchains](https://github.com/stnolting/riscv-gcc-prebuilt) | [](https://github.com/stnolting/riscv-gcc-prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) |
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| [Pre-built toolchains](https://github.com/stnolting/riscv-gcc-prebuilt) | [](https://github.com/stnolting/riscv-gcc-prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) |
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| [RISC-V architecture test](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md) | [](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml) |
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| [RISC-V architecture test](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md) | [](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml) |
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## Features
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## Features
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| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 2465 (12%) | 1912 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
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| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 2465 (12%) | 1912 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
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**_Notes_**
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**_Notes_**
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* The "default" implementation strategy of the according toolchain is used.
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* The "default" implementation strategy of the according toolchain is used.
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* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).
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* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).
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The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
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* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
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* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
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* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
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* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
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bootloader to store and automatically boot an application program after reset (both tested successfully).
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bootloader to store and automatically boot an application program after reset (both tested successfully).
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* The setups with `PMP` implement 2 regions with a minimal granularity of 64kB.
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* The setups with `PMP` implement 2 regions with a minimal granularity of 64kB.
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* No HPM counters are implemented.
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* No HPM counters are implemented.
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This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
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This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
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[:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
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[:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
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### 0. Build the Documentation
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This step is optional since there are pre-built versions of the [processor data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
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and the [software documentation](https://stnolting.github.io/neorv32/files.html). If you want to build the documentation by yourself:
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**NEORV32 Data Sheet**
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To build the data sheet open a console and navigate to the project's `docs` folder. Run `$ sh make_datasheet.sh` (make sure `asciidoctor-pdf` is installed).
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This will take all the `asciidoc` sources from [`docs/src_adoc`](https://github.com/stnolting/neorv32/blob/master/docs/src_adoc) to generate `docs/NEORV32.pdf`.
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**Software Framework Documentation**
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Make sure `doxygen` is installed. Open a console and navigate to the project's `docs` folder and run `$ doxygen Doxyfile`. This will create (if not already there)
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a new folder `docs/doxygen_build/html` where doxygen will generate the HTML-based documentation pages. Open `docs/doxygen_build/html/files.html` to get started.
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### 1. Get the Toolchain
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### 1. Get the Toolchain
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At first you need a **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
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At first you need a **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
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and build the toolchain by yourself, or you can download a prebuilt one and install it.
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and build the toolchain by yourself, or you can download a prebuilt one and install it.
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