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| Project component | CI status |
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| Project component | CI status |
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|:----------------- |:----------|
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|:----------------- |:----------|
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| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) |
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| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) |
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| [SW Framework Documentation (online at GH-pages)](https://stnolting.github.io/neorv32/files.html) | [](https://stnolting.github.io/neorv32/files.html) |
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| [SW Framework Documentation (online at GH-pages)](https://stnolting.github.io/neorv32/files.html) | [](https://stnolting.github.io/neorv32/files.html) |
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| Build data sheet from `asciidoc` sources | [](https://github.com/stnolting/neorv32/actions/workflows/build_datasheet.yml) |
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| Build data sheet from [`asciidoc` sources](https://github.com/stnolting/neorv32/blob/master/docs/src_adoc) | [](https://github.com/stnolting/neorv32/actions/workflows/build_datasheet.yml) |
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| [Pre-built toolchains](https://github.com/stnolting/riscv-gcc-prebuilt) | [](https://github.com/stnolting/riscv-gcc-prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) |
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| [Pre-built toolchains](https://github.com/stnolting/riscv-gcc-prebuilt) | [](https://github.com/stnolting/riscv-gcc-prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) |
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| [RISC-V architecture test](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md) | [](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml) |
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| [RISC-V architecture test](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md) | [](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml) |
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## Features
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## Features
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* Store address misaligned
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* Store address misaligned
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* Store access fault (via unacknowledged bus access after timeout)
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* Store access fault (via unacknowledged bus access after timeout)
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* Environment call from U-mode (via `ecall` instruction in user mode)
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* Environment call from U-mode (via `ecall` instruction in user mode)
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* Environment call from M-mode (via `ecall` instruction in machine mode)
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* Environment call from M-mode (via `ecall` instruction in machine mode)
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* Supported interrupts:
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* Supported interrupts:
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* RISC-V non-maskable interrupt `nmi` (via external signal)
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* RISC-V machine timer interrupt `mti` (via processor-internal MTIME unit *or* external signal)
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* RISC-V machine timer interrupt `mti` (via processor-internal MTIME unit *or* external signal)
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* RISC-V machine software interrupt `msi` (via external signal)
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* RISC-V machine software interrupt `msi` (via external signal)
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* RISC-V machine external interrupt `mei` (via external signal)
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* RISC-V machine external interrupt `mei` (via external signal)
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* 16 fast interrupt requests, 6+1 available for custom usage
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* 16 fast interrupt requests, 6+1 available for custom usage
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### :warning: Non-RISC-V-Compatible Issues and Limitations
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### :warning: Non-RISC-V-Compatible Issues and Limitations
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* CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus interface provides big- and little-endian configurations
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* CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus interface provides big- and little-endian configurations
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* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
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* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
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* `mip` CSR is read-only - pending IRQs can be cleared using `mie`
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* The physical memory protection (**PMP**) only supports `NAPOT` mode yet and a minimal granularity of 8 bytes
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* The physical memory protection (**PMP**) only supports `NAPOT` mode yet and a minimal granularity of 8 bytes
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* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all remaining AMO operations
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* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all remaining AMO operations
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### NEORV32 Processor-Internal Peripherals and Memories
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### NEORV32 Processor-Internal Peripherals and Memories
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Results generated for hardware version [`1.5.3.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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Results generated for hardware version [`1.5.4.9`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
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(mandatory core modules in **bold**).
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| Module | Description | LEs | FFs | Memory bits | DSPs (9-bit) |
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| Module | Description | LEs | FFs | Memory bits | DSPs (9-bit) |
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|:----------|:-----------------------------------------------------|----:|----:|------------:|-------------:|
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|:--------------|:----------------------------------------------------|----:|----:|------------:|-------------:|
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| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
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| Boot ROM | Bootloader ROM (4kB) | 3 | 1 | 32768 | 0 |
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| BUSSWITCH | Bus mux for CPU instr. & data interfaces | 65 | 8 | 0 | 0 |
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| **BUSKEEPER** | Processor-internal bus monitor | 11 | 6 | 0 | 0 |
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| i-CACHE | Proc.-int. nstruction cache (default 1x4x64 bytes) | 234 | 156 | 8 192 | 0 |
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| **BUSSWITCH** | Bus mux for CPU instr. and data interface | 49 | 8 | 0 | 0 |
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| CFS | Custom functions subsystem | - | - | - | - |
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| CFS | Custom functions subsystem | - | - | - | - |
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| DMEM | Processor-internal data memory (default 8kB) | 6 | 2 | 65 536 | 0 |
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| DMEM | Processor-internal data memory (8kB) | 18 | 2 | 65536 | 0 |
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| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0 |
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| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0 |
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| IMEM | Processor-internal instruction memory (default 16kb) | 6 | 2 | 131 072 | 0 |
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| iCACHE | Instruction cache (1x4 blocks, 256 bytes per block) | 220 | 154 | 8192 | 0 |
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| MTIME | Machine system timer | 274 | 166 | 0 | 0 |
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| IMEM | Processor-internal instruction memory (16kB) | 6 | 2 | 131072 | 0 |
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| MTIME | Machine system timer | 289 | 200 | 0 | 0 |
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| NCO | Numerically-controlled oscillator | 254 | 226 | 0 | 0 |
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| NCO | Numerically-controlled oscillator | 254 | 226 | 0 | 0 |
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| NEOLED | Smart LED Interface (NeoPixel-compatibile) [4x FIFO] | 347 | 309 | 0 | 0 |
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| NEOLED | Smart LED Interface (NeoPixel/WS28128) [4xFIFO] | 347 | 309 | 0 | 0 |
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| PWM | Pulse-width modulation controller | 71 | 69 | 0 | 0 |
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| PWM | Pulse_width modulation controller | 71 | 69 | 0 | 0 |
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| SPI | Serial peripheral interface | 138 | 124 | 0 | 0 |
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| SPI | Serial peripheral interface | 138 | 124 | 0 | 0 |
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| SYSINFO | System configuration information memory | 11 | 10 | 0 | 0 |
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| **SYSINFO** | System configuration information memory | 10 | 10 | 0 | 0 |
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| TRNG | True random number generator | 132 | 105 | 0 | 0 |
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| TRNG | True random number generator | 132 | 105 | 0 | 0 |
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| TWI | Two-wire interface | 77 | 46 | 0 | 0 |
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| TWI | Two-wire interface | 77 | 44 | 0 | 0 |
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| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 176 | 132 | 0 | 0 |
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| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 176 | 132 | 0 | 0 |
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| WDT | Watchdog timer | 60 | 45 | 0 | 0 |
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| WDT | Watchdog timer | 60 | 45 | 0 | 0 |
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| WISHBONE | External memory interface | 129 | 104 | 0 | 0 |
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| WISHBONE | External memory interface | 129 | 104 | 0 | 0 |
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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