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[![GitHub Pages](https://img.shields.io/website.svg?label=stnolting.github.io%2Fneorv32&longCache=true&style=flat-square&url=http%3A%2F%2Fstnolting.github.io%2Fneorv32%2Findex.html&logo=GitHub)](https://stnolting.github.io/neorv32)
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[![Processor](https://img.shields.io/github/workflow/status/stnolting/neorv32/Processor/master?longCache=true&style=flat-square&label=Processor&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
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[![riscv-arch-test](https://img.shields.io/github/workflow/status/stnolting/neorv32/riscv-arch-test/master?longCache=true&style=flat-square&label=riscv-arch-test&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test)
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[![Documentation](https://img.shields.io/github/workflow/status/stnolting/neorv32/Documentation/master?longCache=true&style=flat-square&label=Documentation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
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[![Implementation](https://img.shields.io/github/workflow/status/stnolting/neorv32/Implementation/master?longCache=true&style=flat-square&label=Implementation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AImplementation)
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[![NEORV32](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_logo_dark.png)](https://github.com/stnolting/neorv32)
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[![NEORV32](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_logo_dark.png)](https://github.com/stnolting/neorv32)
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# The NEORV32 RISC-V Processor
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# The NEORV32 RISC-V Processor
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[![Processor Check](https://github.com/stnolting/neorv32/workflows/Processor%20Check/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22)
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[![license](https://img.shields.io/github/license/stnolting/neorv32?longCache=true&style=flat-square)](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[![riscv-arch-test](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml/badge.svg)](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml)
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[![release](https://img.shields.io/github/v/release/stnolting/neorv32?longCache=true&style=flat-square&logo=GitHub)](https://github.com/stnolting/neorv32/releases)
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[![license](https://img.shields.io/github/license/stnolting/neorv32)](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[![datasheet (pdf)](https://img.shields.io/badge/data%20sheet-PDF-ffbd00?longCache=true&style=flat-square&logo=asciidoctor)](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[![release](https://img.shields.io/github/v/release/stnolting/neorv32)](https://github.com/stnolting/neorv32/releases)
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[![datasheet (html)](https://img.shields.io/badge/data%20sheet-HTML-ffbd00?longCache=true&style=flat-square&logo=asciidoctor)](https://stnolting.github.io/neorv32)
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[![datasheet](https://img.shields.io/badge/data%20sheet-NEORV32.pdf-ffbd00)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
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[![doxygen](https://img.shields.io/badge/doxygen-HTML-ffbd00?longCache=true&style=flat-square&logo=Doxygen)](https://stnolting.github.io/neorv32/sw/files.html)
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* [Overview](#Overview)
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* [Overview](#Overview)
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* [Status](#Status)
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* [CPU Features](#NEORV32-CPU-Features)
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* [Features](#Features)
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* [Processor/SoC Features](#NEORV32-Processor-Features)
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* [Software Framework](#NEORV32-Software-Framework)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [Performance](#Performance)
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* [Performance](#Performance)
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* [Top Entities](#Top-Entities)
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* [**Getting Started**](#Getting-Started)
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* [**Getting Started**](#Getting-Started)
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* [Contribute/Feedback/Questions](#ContributeFeedbackQuestions)
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* [Legal](#Legal)
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* [Legal](#Legal)
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## Overview
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## Overview
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![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_processor.png)
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![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_processor.png)
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU.
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on the RISC-V NEORV32 CPU. The processor is intended as auxiliary processor in larger SoC
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The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone
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designs or as *ready-to-go* stand-alone custom microcontroller.
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custom / customizable microcontroller.
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:books: For detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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:books: For detailed information take a look at the [NEORV32 documentation /datasheet (online at GitHub-pages)](https://stnolting.github.io/neorv32/).
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The `asciidoc` sources can be found in [`docs/src_adoc`](https://github.com/stnolting/neorv32/blob/master/docs/src_adoc). The latest automatic build
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The `asciidoc` sources can be found in [`docs/src_adoc`](https://github.com/stnolting/neorv32/blob/master/docs/src_adoc).
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can be downloaded as artifacts from the [_Build Data Sheet_ GitHub workflow](https://github.com/stnolting/neorv32/actions/workflows/build_datasheet.yml).
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The *doxygen*-based documentation of the *software framework* is also available online
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The doxygen-based documentation of the *software framework* is available online at [GitHub-pages](https://stnolting.github.io/neorv32/files.html).
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at [GitHub-pages](https://stnolting.github.io/neorv32/sw/files.html).
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:label: The project’s change log is available as [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) in the root directory of this repository.
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:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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To see the changes between *stable* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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To see the changes between *official* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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:rocket: The [`boards`](https://github.com/stnolting/neorv32/tree/master/boards) folder provides exemplary setups targeting various FPGA boards to get you started.
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:package: The [`boards`](https://github.com/stnolting/neorv32/tree/master/boards) folder provides exemplary EDA setups targeting
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various FPGA boards to get you started.
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:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
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:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
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**TODOs**, features being **planned** and **work-in-progress**.
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**TODOs**, features being **planned** and **work-in-progress**.
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:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a [new discussion](https://github.com/stnolting/neorv32/discussions)
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:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
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if you have questions, comments, ideas or bug-fixes. Check out how to [contribute](#ContributeFeedbackQuestions).
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[new discussion](https://github.com/stnolting/neorv32/discussions) if you have questions, comments, ideas or bug-fixes.
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Check out how to contribute in [`CONTRIBUTE.md`](https://github.com/stnolting/neorv32/blob/master/CONTRIBUTING.md).
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### Key Features
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* RISC-V 32-bit `rv32` [**NEORV32 CPU**](#NEORV32-CPU-Features), compatible to
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* subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)
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* subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)
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* the [official RISC-V architecture tests](#Status) (*passing*)
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* Configurable RISC-V-compatible CPU extensions
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* [`A`](#A---Atomic-memory-access-extension) - atomic memory access instructions (optional)
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* [`B`](#B---Bit-manipulation-instructions-extension) - Bit manipulation instructions (optional) :construction:
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* [`C`](#C---Compressed-instructions-extension) - compressed instructions (16-bit) (optional)
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* [`E`](#E---Embedded-CPU-version-extension) - embedded CPU (reduced register file size) (optional)
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* [`I`](#I---Base-integer-instruction-set) - base integer instruction set (always enabled)
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* [`M`](#M---Integer-multiplication-and-division-hardware-extension) - integer multiplication and division hardware (optional)
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* [`U`](#U---Privileged-architecture---User-mode-extension) - less-privileged *user mode* (optional)
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* [`X`](#X---NEORV32-specific-CPU-extensions) - NEORV32-specific extensions (always enabled)
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* [`Zfinx`](#Zfinx---Single-precision-floating-point-extension) - Single-precision floating-point extensions (optional)
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* [`Zicsr`](#Zicsr---Privileged-architecture---CSR-access-extension) - control and status register access instructions (+ exception/irq system) (optional)
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* [`Zifencei`](#Zifencei---Instruction-stream-synchronization-extension) - instruction stream synchronization (optional)
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* [`PMP`](#PMP---Privileged-architecture---Physical-memory-protection) - physical memory protection (optional)
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* [`HPM`](#HPM---Privileged-architecture---Hardware-performance-monitors) - hardware performance monitors (optional)
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* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
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* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
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* timers (watch dog, RISC-V-compatible machine timer)
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* serial interfaces (SPI, TWI, UARTs)
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* general purpose IO and PWM channels
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* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
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* dedicated NeoPixel(TM) LED interface
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* subsystem for custom co-processors
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* [more ...](#NEORV32-Processor-Features)
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* Software framework
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* core libraries for high-level usage of the provided functions and peripherals
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* application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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* GCC-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
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* bootloader with UART interface console
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* runtime environment
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* several example programs
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* [doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/Doxyfile) software documentation: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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* [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
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* [**Full-blown data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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* Completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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* Fully synchronous design, no latches, no gated clocks
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* Small hardware footprint and high operating frequency
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### Design Principles
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* From zero to *hello_world*: Completely open source and documented.
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* Plain VHDL without technology-specific parts like attributes, macros or primitives.
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* Easy to use – working out of the box.
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* Clean synchronous design, no wacky combinatorial interfaces.
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* Be as small as possible – but with a reasonable size-performance trade-off.
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* Be as RISC-V-compliant as possible.
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k low-power FPGA running at 22+ MHz.
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### Status
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The processor is [synthesizable](#FPGA-Implementation-Results) (tested on *real hardware* using Intel Quartus Prime, Xilinx Vivado and Lattice Radiant) and can successfully execute
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark) and the custom
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NEORV32 processor check ([`sw/example/cpu_test`](https://github.com/stnolting/neorv32/tree/master/sw/example/cpu_test), see the status report in the according
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[GitHub workflow](https://github.com/stnolting/neorv32/actions/workflows/processor-check.yml)).
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**RISC-V Architecture Tests**: The processor passes the official `rv32_m/C`, `rv32_m/I`, `rv32_m/M`, `rv32_m/privilege` and `rv32_m/Zifencei`
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[riscv-arch-test](https://github.com/riscv/riscv-arch-test) tests. More information regarding the NEORV32 port of the riscv-arch-test test framework can be found in
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[`riscv-arch-test/README.md`](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md).
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| Project component | CI status |
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|:----------------- |:----------|
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| [NEORV32 processor](https://github.com/stnolting/neorv32) | [![Processor Check](https://github.com/stnolting/neorv32/workflows/Processor%20Check/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) |
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| [SW Framework Documentation (online at GH-pages)](https://stnolting.github.io/neorv32/files.html) | [![Doc@GitHub-pages](https://github.com/stnolting/neorv32/workflows/Deploy%20SW%20Framework%20Documentation%20to%20GitHub-Pages/badge.svg)](https://stnolting.github.io/neorv32/files.html) |
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| Build data sheet from [`asciidoc` sources](https://github.com/stnolting/neorv32/blob/master/docs/src_adoc) | [![Build Data Sheet](https://github.com/stnolting/neorv32/actions/workflows/build_datasheet.yml/badge.svg)](https://github.com/stnolting/neorv32/actions/workflows/build_datasheet.yml) |
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| [Pre-built toolchains](https://github.com/stnolting/riscv-gcc-prebuilt) | [![Test Toolchains](https://github.com/stnolting/riscv-gcc-prebuilt/workflows/Test%20Toolchains/badge.svg)](https://github.com/stnolting/riscv-gcc-prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) |
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| [RISC-V architecture test](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md) | [![riscv-arch-test](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml/badge.svg)](https://github.com/stnolting/neorv32/actions/workflows/riscv-arch-test.yml) |
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## Features
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The full-blown data sheet of the NEORV32 Processor and CPU is available as pdf file:
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[:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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### NEORV32 Processor Features
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The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
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|
is highly customizable via the processor's top generics and already provides the following *optional* modules:
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* processor-internal data and instruction memories (**DMEM** / **IMEM**) & cache (**iCACHE**)
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* bootloader (**BOOTLDROM**) with UART console and automatic application boot from SPI flash option
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* machine system timer (**MTIME**), RISC-V-compatible
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* watchdog timer (**WDT**)
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* two independent universal asynchronous receivers and transmitters (**UART0** & **UART1**) with optional hardware flow control (RTS/CTS)
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* 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
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* two wire serial interface controller (**TWI**), with optional clock-stretching, compatible to the I²C standard
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* general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
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* 32-bit external bus interface, Wishbone b4 compatible (**WISHBONE**)
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* wrapper for **AXI4-Lite Master Interface** (see [AXI Connectivity](#AXI4-Connectivity))
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* PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
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* ring-oscillator-based true random number generator (**TRNG**)
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* custom functions subsystem (**CFS**) for tightly-coupled custom co-processor extensions
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* numerically-controlled oscillator (**NCO**) with three independent channels
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* smart LED interface (**NEOLED**) - WS2812 / NeoPixel(c) compatible
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* system configuration information memory to check hardware configuration by software (**SYSINFO**)
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### NEORV32 CPU Features
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The NEORV32 CPU implements the
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[official RISC-V specifications (2.2)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
|
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[RISC-V privileged architecture specifications (1.12-draft)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf)
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- tested via the [official riscv-arch-test Test Framework](https://github.com/riscv/riscv-arch-test)
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(see [`riscv-arch-test/README`](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md)).
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More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in
|
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the [:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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#### General Features
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* Modified Harvard architecture (separate CPU interfaces for data and instructions; NEORV32 processor: Single processor-internal bus via I/D mux)
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* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme
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* No hardware support of unaligned accesses - they will trigger an exception
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* BIG-ENDIAN byte-order, processor's external memory interface allows endianness configuration to connect to system with different endianness
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* All reserved or unimplemented instructions will raise an illegal instruction exception
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* Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)
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* Official [RISC-V open-source architecture ID](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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#### `A` - Atomic memory access extension
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* Supported instructions: `LR.W` (load-reservate) `SC.W` (store-conditional)
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[[back to top](#The-NEORV32-RISC-V-Processor)]
|
:rocket: Check out the [quick links below](#Getting-Started) or directly jump to the documentation's
|
|
[*Let's Get It Started!*](https://stnolting.github.io/neorv32/#_lets_get_it_started) section to get started
|
|
setting up your NEORV32 setup!
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#### `B` - Bit manipulation instructions extension
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### Project Key Features
|
|
|
* :construction: **work-in-progress** :construction:
|
* [CPU](#NEORV32-CPU-Features) plus [Processor/SoC](#NEORV32-Processor-Features) plus [Software Framework](#NEORV32-Software-Framework)
|
* :warning: this extension has not been officially ratified yet!
|
* completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
|
* :books: more information can be found here: [RISC-V `B` spec.](https://github.com/riscv/riscv-bitmanip)
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* fully synchronous design, no latches, no gated clocks
|
* Compatible to [v0.94-draft](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/bitmanip-draft.pdf) of the bit manipulation spec
|
* be as small as possible (while being as RISC-V-compliant as possible) – but with a reasonable size-performance trade-off
|
* Software support via intrinsic library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation))
|
(the processor has to fit in a Lattice iCE40 UltraPlus 5k low-power FPGA running at 22+ MHz)
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* `Zbb` base instruction set: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR[I]` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`)
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* from zero to `printf("hello world!");` - completely open source and documented
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* `Zbs` single-bit instructions: `SBSET[I]` `SBCLR[I]` `SBINV[I]` `SBEXT[I]`
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* easy to use even for FPGA/RISC-V starters – intended to work *out of the box*
|
* `Zba` shifted-add instructions: `SH1ADD` `SH2ADD` `SH3ADD`
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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#### `C` - Compressed instructions extension
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* ALU instructions: `C.ADDI4SPN` `C.ADD[I]` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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* System instructions: `C.EBREAK` (requires `Zicsr` extension)
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* Pseudo-instructions are not listed
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## NEORV32 CPU Features
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:books: In-depth detailed information regarding the CPU can be found in the
|
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[online documentation - _"NEORV32 Central Processing Unit"_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu).
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|
#### `E` - Embedded CPU version extension
|
The CPU (top entity: [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd))
|
|
implements the RISC-V 32-bit `rv32` ISA with optional extensions. It is compatible to a subset of the
|
* Reduced register file (only the 16 lowest registers are implemented)
|
*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
|
|
and a subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
The CPU [passes](https://stnolting.github.io/neorv32/#_risc_v_compatibility) the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test)
|
|
(see [`riscv-arch-test/README`](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md)).
|
|
|
#### `I` - Base integer instruction set
|
|
|
|
* ALU instructions: `LUI` `AUIPC` `ADD[I]` `SLT[I][U]` `XOR[I]` `OR[I]` `AND[I]` `SLL[I]` `SRL[I]` `SRA[I]` `SUB`
|
|
* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
|
|
* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
|
|
* System instructions: `ECALL` `EBREAK` `FENCE`
|
|
* Pseudo-instructions are not listed
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
#### `M` - Integer multiplication and division hardware extension
|
|
|
|
* Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
|
|
* Division instructions: `DIV` `DIVU` `REM` `REMU`
|
|
* By default, the multiplier and divider cores use an iterative bit-serial processing scheme
|
|
* Multiplications can be mapped to DSPs via the `FAST_MUL_EN` generic to increase performance
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
#### `U` - Privileged architecture - User mode extension
|
|
|
|
* Requires `Zicsr` extension
|
|
* Privilege levels: `M` (machine mode) + less-privileged `U` (user mode)
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
#### `X` - NEORV32-specific CPU extensions
|
|
|
|
* The NEORV32-specific extensions are always enabled and are indicated via the `X` bit set in the `misa` CSR.
|
|
* 16 *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
|
|
* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`)
|
|
* All undefined/umimplemented/malformed/illegal instructions do raise an illegal instruction exception
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
#### `Zfinx` - Single-precision floating-point extension
|
|
|
|
* :warning: this extension has not been officially ratified yet!
|
In order to provide a reduced-size setup the NEORV32 CPU implements a two-stages pipeline, where each stage
|
* :books: more information can be found here: [RISC-V `Zfinx` spec.](https://github.com/riscv/riscv-zfinx)
|
uses a multi-cycle processing scheme. Instruction and data accesses are conducted via independant bus interfaces,
|
* Software support via intrinsic library (see [`sw/example/floating_point_test`](https://github.com/stnolting/neorv32/tree/master/sw/example/floating_point_test))
|
that are multiplexed into a single SoC-bus ("modified Harvard architecture"). As a special execution safety feature,
|
* Fused multiply-add instructions (`F[N]MADD.S` & `F[N)MSUB.S`) are **not** supported!
|
all reserved or unimplemented instructions do raise an exception. Furthermore, the CPU was assigned an *official*
|
* Computational instructions: `FADD.S` `FSUB.S` `FMUL.S` `FSGNJ[N/X].S` `FCLASS.S` ~~`FDIV.S`~~ ~~`FSQRT.S`~~
|
RISC-V open-source [architecture ID](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)
|
* Comparison instructions: `FMIN.S` `FMAX.S` `FEQ.S` `FLT.S` `FLE.S`
|
|
* Conversion instructions: `FCVT.W.S` `FCVT.WU.S` `FCVT.S.W` `FCVT.S.WU`
|
RISC-V-compatible **ISA extensions** currently provided by the NEORV32 (:books: [see full list](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions)):
|
* Additional CSRs: `fcsr` `frm` `fflags`
|
* `A` - atomic memory access instructions (optional)
|
|
* `B` - bit manipulation instructions (subset, optional, still experimental)
|
|
* `C` - compressed 16-bit instructions (optional)
|
|
* `E` - embedded CPU (reduced register file size) (optional)
|
|
* `I` - base integer instruction set (always enabled)
|
|
* `M` - integer multiplication and division hardware (optional)
|
|
* `U` - less-privileged `user` mode in combintation with the standard `machine` mode (optional)
|
|
* `X` - NEORV32-specific extensions (always enabled)
|
|
* `Zfinx` - IEEE-754 single-precision floating-point extensions (optional)
|
|
* `Zicsr` - control and status register access instructions (+ exception/irq system) (optional)
|
|
* `Zifencei` - instruction stream synchronization (optional)
|
|
* `PMP` - physical memory protection (optional)
|
|
* `HPM` - hardware performance monitors (optional)
|
|
* `DB` - RISC-V CPU debug mode (optional)
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
#### `Zicsr` - Privileged architecture - CSR access extension
|
|
|
|
* Privilege levels: `M-mode` (Machine mode)
|
|
* CSR access instructions: `CSRRW[I]` `CSRRS[I]` `CSRRC[I]`
|
|
* System instructions: `MRET` `WFI`
|
|
* Pseudo-instructions are not listed
|
|
* Counter CSRs: `[m]cycle[h]` `[m]instret[m]` `time[h]` `[m]hpmcounter*[h]`(3..31, configurable) `mcounteren` `mcountinhibit` `mhpmevent*`(3..31, configurable)
|
|
* Machine CSRs: `mstatus[h]` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
|
|
* Supported (sync.) exceptions (implementing the RISC-V specs):
|
|
* Misaligned instruction address
|
|
* Instruction access fault (via timeout/error after unacknowledged bus access)
|
|
* Illegal instruction
|
|
* Breakpoint (via `ebreak` instruction)
|
|
* Load address misaligned
|
|
* Load access fault (via timeout/error after unacknowledged bus access)
|
|
* Store address misaligned
|
|
* Store access fault (via unacknowledged bus access after timeout)
|
|
* Environment call from U-mode (via `ecall` instruction in user mode)
|
|
* Environment call from M-mode (via `ecall` instruction in machine mode)
|
|
* Supported interrupts:
|
|
* RISC-V non-maskable interrupt `nmi` (via external signal)
|
|
* RISC-V machine timer interrupt `mti` (via processor-internal MTIME unit *or* external signal)
|
|
* RISC-V machine software interrupt `msi` (via external signal)
|
|
* RISC-V machine external interrupt `mei` (via external signal)
|
|
* 16 fast interrupt requests, 6+1 available for custom usage
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
#### `Zifencei` - Instruction stream synchronization extension
|
## NEORV32 Processor Features
|
|
|
|
:books: In-depth detailed information regarding the processor/SoC and the provided optional module can be found in the
|
|
[online documentation - _"NEORV32 Processors (SoC)"_](https://stnolting.github.io/neorv32/#_neorv32_processor_soc).
|
|
|
|
The NEORV32 Processor (top entity: [`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd))
|
|
provides a full-featured SoC build around the NEORV32 CPU. It is highly configurable to allow
|
|
a flexible customization according to your needs.
|
|
|
|
Included SoC modules:
|
|
* processor-internal data and instruction memories ([DMEM](https://stnolting.github.io/neorv32/#_data_memory_dmem) /
|
|
[IMEM](https://stnolting.github.io/neorv32/#_instruction_memory_imem)) &
|
|
cache ([iCACHE](https://stnolting.github.io/neorv32/#_processor_internal_instruction_cache_icache))
|
|
* bootloader ([BOOTLDROM](https://stnolting.github.io/neorv32/#_bootloader_rom_bootrom)) with UART console and automatic
|
|
application boot from external SPI flash option
|
|
* machine system timer ([MTIME](https://stnolting.github.io/neorv32/#_machine_system_timer_mtime)), RISC-V-compatible
|
|
* watchdog timer ([WDT](https://stnolting.github.io/neorv32/#_watchdog_timer_wdt))
|
|
* two independent universal asynchronous receivers and transmitters
|
|
([UART0](https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0) and
|
|
[UART1](https://stnolting.github.io/neorv32/#_secondary_universal_asynchronous_receiver_and_transmitter_uart1))
|
|
with optional RTS/CTS hardware flow control
|
|
* 8/16/24/32-bit serial peripheral interface controller
|
|
([SPI](https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi)) with 8 dedicated chip select lines
|
|
* two wire serial interface controller ([TWI](https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi))
|
|
supporting clock-stretching, compatible to the I²C standard
|
|
* general purpose parallel IO port ([GPIO](https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio)),
|
|
32xOut & 32xIn with pin-change interrupt
|
|
* 32-bit external bus interface, Wishbone b4 compatible
|
|
([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
|
|
* wrapper for AXI4-Lite Master Interface
|
|
* PWM controller with 4 channels and 8-bit duty cycle resolution
|
|
([PWM](https://stnolting.github.io/neorv32/#_pulse_width_modulation_controller_pwm))
|
|
* ring-oscillator-based *true random* number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
|
|
* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
|
|
for tightly-coupled custom co-processor extensions
|
|
* numerically-controlled oscillator ([NCO](https://stnolting.github.io/neorv32/#_numerically_controlled_oscillator_nco))
|
|
with three independent channels
|
|
* smart LED interface ([NEOLED](https://stnolting.github.io/neorv32/#_smart_led_interface_neoled))
|
|
to directly drive WS2812-compatible (*NeoPixel(TM)*) LEDs
|
|
* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) via JTGA - compatible to
|
|
the [*Minimal RISC-V Debug Specification Version 0.13.2*](https://github.com/riscv/riscv-debug-spec)
|
|
and compatible with the *OpenOCD* and *gdb*
|
|
* alternative [top entities/wrappers](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) available
|
|
|
* System instructions: `FENCE.I` (among others, used to clear and reload instruction cache)
|
:information_source: It is recommended to use the processor setup even if you want to **use the CPU in stand-alone mode**. Simply disable all the processor-internal
|
|
modules via the generics and you will get a "CPU wrapper" that already provides a minimal CPU environment and an external memory interface (like AXI4).
|
|
This setup also allows to further use the default bootloader and software framework. From this base you can start building your own processor system.
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
#### `PMP` - Privileged architecture - Physical memory protection
|
|
|
|
* Requires `Zicsr` extension
|
|
* Configurable number of regions (0..63)
|
|
* Additional machine CSRs: `pmpcfg*`(0..15) `pmpaddr*`(0..63)
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
## NEORV32 Software Framework
|
|
|
|
:books: In-depth detailed information regarding the software framework can be found in the
|
|
[online documentation - _"Software Framework"_](https://stnolting.github.io/neorv32/#_software_framework).
|
|
|
#### `HPM` - Privileged architecture - Hardware performance monitors
|
* [core libraries](https://github.com/stnolting/neorv32/tree/master/sw/lib) for high-level usage of the provided functions and peripherals
|
|
* application compilation based on GNU makefiles
|
* Requires `Zicsr` extension
|
* gcc-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
|
* Configurable number of counters (0..29)
|
* bootloader with UART interface console
|
* Additional machine CSRs: `mhpmevent*`(3..31) `[m]hpmcounter*[h]`(3..31)
|
* runtime environment for handling traps
|
|
* several [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) to get started including CoreMark, FreeRTOS and *Conway's Game of Life*
|
|
* `doxygen`-based documentation, available on [GitHub pages](https://stnolting.github.io/neorv32/sw/files.html)
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### :warning: Non-RISC-V-Compatible Issues and Limitations
|
|
|
|
* CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus interface provides big- and little-endian configurations
|
|
* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
|
|
* `mip` CSR is read-only - pending IRQs can be cleared using `mie`
|
|
* The physical memory protection (**PMP**) only supports `NAPOT` mode yet and a minimal granularity of 8 bytes
|
|
* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all remaining AMO operations
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
## FPGA Implementation Results
|
|
|
|
:books: More details regarding exemplary FPGA setups including a listing of resource utilization by each SoC module can be found in the
|
|
[online documentation - _"FPGA Implementation Results"_](https://stnolting.github.io/neorv32/#_fpga_implementation_results).
|
|
|
|
|
## FPGA Implementation Results
|
|
|
|
### NEORV32 CPU
|
### NEORV32 CPU
|
|
|
This chapter shows exemplary implementation results of the NEORV32 CPU for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
|
Implementation results for exemplary CPU configuration generated for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
|
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing
|
a DE0-nano board using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing information is derived
|
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
|
from the Timing Analyzer / Slow 1200mV 0C Model. No constraints were used at all.
|
of the CPU's generics is assumed (e.g. no physical memory protection, no hardware performance monitors).
|
|
No constraints were used at all.
|
|
|
|
Results generated for hardware version [`1.5.3.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.5.3.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs (9-bit) | f_max |
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs (9-bit) | f_max |
|
|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
|
|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
|
| `rv32i` | 980 | 409 | 1024 | 0 | 123 MHz |
|
| `rv32i` | 980 | 409 | 1024 | 0 | 123 MHz |
|
| `rv32i` + `Zicsr` | 1835 | 856 | 1024 | 0 | 124 MHz |
|
| `rv32i` + `Zicsr` | 1835 | 856 | 1024 | 0 | 124 MHz |
|
| `rv32im` + `Zicsr` | 2443 | 1134 | 1024 | 0 | 124 MHz |
|
|
| `rv32imc` + `Zicsr` | 2669 | 1149 | 1024 | 0 | 125 MHz |
|
|
| `rv32imac` + `Zicsr` | 2685 | 1156 | 1024 | 0 | 124 MHz |
|
| `rv32imac` + `Zicsr` | 2685 | 1156 | 1024 | 0 | 124 MHz |
|
| `rv32imac` + `Zicsr` + `u` | 2698 | 1162 | 1024 | 0 | 124 MHz |
|
|
| `rv32imac` + `Zicsr` + `u` + `Zifencei` | 2715 | 1162 | 1024 | 0 | 122 MHz |
|
| `rv32imac` + `Zicsr` + `u` + `Zifencei` | 2715 | 1162 | 1024 | 0 | 122 MHz |
|
| `rv32imac` + `Zicsr` + `u` + `Zifencei` + `Zfinx` | 4004 | 1812 | 1024 | 7 | 121 MHz |
|
| `rv32imac` + `Zicsr` + `u` + `Zifencei` + `Zfinx` | 4004 | 1812 | 1024 | 7 | 121 MHz |
|
|
|
Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max as the according `I` configuration.
|
Setups with enabled `E` (embedded CPU extension) provide the same LUT and FF utilization and identical f_max as the according
|
However, the size of the register file is cut in half.
|
`I` configuration. However, the size of the register file and thus, the embedded memory utilization, is cut in half.
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### NEORV32 Processor-Internal Peripherals and Memories
|
|
|
|
Results generated for hardware version [`1.5.4.9`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
|
|
(mandatory core modules in **bold**).
|
|
|
|
| Module | Description | LEs | FFs | Memory bits | DSPs (9-bit) |
|
|
|:--------------|:----------------------------------------------------|----:|----:|------------:|-------------:|
|
|
| Boot ROM | Bootloader ROM (4kB) | 3 | 1 | 32768 | 0 |
|
|
| **BUSKEEPER** | Processor-internal bus monitor | 11 | 6 | 0 | 0 |
|
|
| **BUSSWITCH** | Bus mux for CPU instr. and data interface | 49 | 8 | 0 | 0 |
|
|
| CFS | Custom functions subsystem | - | - | - | - |
|
|
| DMEM | Processor-internal data memory (8kB) | 18 | 2 | 65536 | 0 |
|
|
| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0 |
|
|
| iCACHE | Instruction cache (1x4 blocks, 256 bytes per block) | 220 | 154 | 8192 | 0 |
|
|
| IMEM | Processor-internal instruction memory (16kB) | 6 | 2 | 131072 | 0 |
|
|
| MTIME | Machine system timer | 289 | 200 | 0 | 0 |
|
|
| NCO | Numerically-controlled oscillator | 254 | 226 | 0 | 0 |
|
|
| NEOLED | Smart LED Interface (NeoPixel/WS28128) [4xFIFO] | 347 | 309 | 0 | 0 |
|
|
| PWM | Pulse_width modulation controller | 71 | 69 | 0 | 0 |
|
|
| SPI | Serial peripheral interface | 138 | 124 | 0 | 0 |
|
|
| **SYSINFO** | System configuration information memory | 10 | 10 | 0 | 0 |
|
|
| TRNG | True random number generator | 132 | 105 | 0 | 0 |
|
|
| TWI | Two-wire interface | 77 | 44 | 0 | 0 |
|
|
| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 176 | 132 | 0 | 0 |
|
|
| WDT | Watchdog timer | 60 | 45 | 0 | 0 |
|
|
| WISHBONE | External memory interface | 129 | 104 | 0 | 0 |
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
### NEORV32 Processor - Exemplary FPGA Setups
|
### NEORV32 Processor
|
|
|
:information_source: Check out the [`boards`](https://github.com/stnolting/neorv32/tree/master/boards) folder for exemplary setups targeting various FPGA boards.
|
:information_source: Check out the [`boards`](https://github.com/stnolting/neorv32/tree/master/boards)
|
|
folder for exemplary setups targeting various FPGA boards.
|
|
|
The following tables show exemplary processor implementation results for different FPGA platforms. The processor setups use *the default peripheral configuration* (like no *CFS* and no *TRNG*),
|
:information_source: The hardware resources used by the processor-internal IO/peripheral modules andmemories is also available in the
|
no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space.
|
[online documentation - _"NEORV32 Central Processing Unit"_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu).
|
|
|
Results generated for hardware version [`1.4.9.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.4.9.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
If not otherwise note, the setups use *the default configuration* (like no *TRNG*),
|
|
no external memory interface and only internal instruction and data memories
|
|
(IMEM uses 16kB and DMEM uses 8kB memory space).
|
|
|
| Vendor | FPGA | Board | Toolchain | CPU Configuration | LUT / LE | FF / REG | DSP (9-bit) | Memory Bits | BRAM / EBR | SPRAM | Frequency |
|
| Vendor | FPGA | Board | Toolchain | CPU Configuration | LUT / LE | FF / REG | DSP (9-bit) | Memory Bits | BRAM / EBR | SPRAM | Frequency |
|
|:--------|:----------------------------------|:-----------------|:---------------------------|:-----------------------------------------------|:-----------|:-----------|:------------|:-------------|:-----------|:---------|--------------:|
|
|:--------|:----------------------------------|:-----------------|:---------------------------|:----------------------------------|:-----------|:-----------|:------------|:-------------|:-----------|:---------|--------------:|
|
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 20.1 | `rv32imc` + `u` + `Zicsr` + `Zifencei` | 3813 (17%) | 1904 (8%) | 0 (0%) | 231424 (38%) | - | - | 119 MHz |
|
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 20.1 | `rv32imcu_Zicsr_Zifencei` | 3813 (17%) | 1904 (8%) | 0 (0%) | 231424 (38%) | - | - | 119 MHz |
|
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (Synplify Pro) | `rv32ic` + `u` + `Zicsr` + `Zifencei` | 4397 (83%) | 1679 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.15 MHz |
|
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | [`boards/UPduino_v3`](https://github.com/stnolting/neorv32/tree/master/boards/UPduino_v3) | Radiant 2.1 (LSE) | `rv32imac_Zicsr` | 5123 (97%) | 1972 (37%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 24 MHz |
|
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 2465 (12%) | 1912 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
|
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | `rv32imcu_Zicsr_Zifencei` + `PMP` | 2465 (12%) | 1912 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
|
|
|
**_Notes_**
|
|
* The "default" implementation strategy of the according toolchain is used.
|
|
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).
|
|
* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
|
|
* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
|
|
bootloader to store and automatically boot an application program after reset (both tested successfully).
|
|
* The setups with `PMP` implement 2 regions with a minimal granularity of 64kB.
|
|
* No HPM counters are implemented.
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
## Performance
|
## Performance
|
|
|
### CoreMark Benchmark
|
The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme.
|
|
Hence, each instruction requires several clock cycles to execute (2 cycles for ALU operations, and up to 40 cycles for divisions).
|
The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
|
*By default* the CPU-internal shifter as well as the multiplier and divider of the `M` extension use a bit-serial approach
|
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
|
and require several cycles for completion. The average CPI (cycles per instruction) depends on the instruction mix of a
|
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
|
specific applications and also on the available CPU extensions.
|
|
|
|
The following table shows the performance results(relative CoreMark score and average cycles per instruction) for successfully
|
|
running 2000 iterations of the [CoreMark CPU benchmark](https://www.eembc.org/coremark), which reflects a pretty good "real-life" work load.
|
|
The source files are available in [sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark).
|
|
|
~~~
|
~~~
|
**Configuration**
|
**CoreMark Setup**
|
Hardware: 32kB IMEM, 8kB DMEM, no caches, 100MHz clock
|
Hardware: 32kB IMEM, 8kB DMEM, no caches, 100MHz clock
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
Compiler flags: default, see makefile
|
Compiler flags: default, see makefile
|
Optimization: -O3
|
Optimization: -O3
|
Peripherals: UART for printing the results
|
Peripherals: UART for printing the results
|
~~~
|
~~~
|
|
|
Results generated for hardware version [`1.4.9.8`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.4.9.8`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
| CPU (including `Zicsr` extension) | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
|
| CPU (including `Zicsr` extension) | Executable Size | CoreMark Score | CoreMarks/MHz | Total Clock Cycles | Executed Instructions | Average CPI |
|
|:--------------------------------------------|:---------------:|:------------:|:--------------:|:-------------:|
|
|:--------------------------------------------|:---------------:|:--------------:|:-------------:|-------------------:|----------------------:|:-----------:|
|
| `rv32i` | 28 756 bytes | `-O3` | 36.36 | **0.3636** |
|
| `rv32i` | 28 756 bytes | 36.36 | **0.3636** | 5595750503 | 1466028607 | **3.82** |
|
| `rv32imc` | 22 008 bytes | `-O3` | 68.97 | **0.6897** |
|
| `rv32imc` | 22 008 bytes | 68.97 | **0.6897** | 2981786734 | 611814918 | **4.87** |
|
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 22 008 bytes | `-O3` | 90.91 | **0.9091** |
|
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 22 008 bytes | 90.91 | **0.9091** | 2265135174 | 611814948 | **3.70** |
|
|
|
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
|
:information_source: The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension
|
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
|
(enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration uses a barrel shifter for
|
|
CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
|
When the `C` extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
### Instruction Cycles
|
|
|
|
The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
|
|
each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
|
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available
|
|
CPU extensions. *By default* the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
|
|
`M` extension use a bit-serial approach and require several cycles for completion.
|
|
|
|
The following table shows the performance results for successfully running 2000 CoreMark
|
|
iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by
|
|
dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)
|
|
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O3`.
|
|
|
|
Results generated for hardware version [`1.4.9.8`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
|
| CPU (including `Zicsr` extension) | Required Clock Cycles | Executed Instructions | Average CPI |
|
|
|:--------------------------------------------|----------------------:|----------------------:|:-----------:|
|
|
| `rv32i` | 5 595 750 503 | 1 466 028 607 | **3.82** |
|
|
| `rv32imc` | 2 981 786 734 | 611 814 918 | **4.87** |
|
|
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 2 265 135 174 | 611 814 948 | **3.70** |
|
|
|
|
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
|
|
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
|
|
|
|
When the `C` extension is enabled branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
|
## Top Entities
|
|
|
|
The top entity of the **NEORV32 Processor** (SoC) is [`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd),
|
|
which provides a Wishbone b4-compatoible bus interface.
|
|
|
|
:information_source: It is recommended to use the processor setup even if you want to **use the CPU in stand-alone mode**. Simply disable all the processor-internal
|
|
modules via the generics and you will get a "CPU wrapper" that already provides a minimal CPU environment and an external memory interface (like AXI4).
|
|
This setup also allows to further use the default bootloader and software framework. From this base you can start building your own processor system.
|
|
|
|
Use the top's generics to configure the system according to your needs. Each generic is initilized with the default configuration.
|
|
Detailed information regarding the interface signals and configuration generics can be found in
|
|
the [:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf).
|
|
|
|
All signals of the top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively
|
|
(except for the processor's TWI signals, which are of type *std_logic*). Leave all unused output ports unconnected and tie all unused
|
|
input ports to zero.
|
|
|
|
**Alternative top entities**, like the simplified ["hello world" test setup](#Create-a-new-Hardware-Project) or CPU/Processor
|
|
wrappers with resolved port signal types (i.e. *std_logic*), can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates).
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
### AXI4 Connectivity
|
|
|
|
Via the [`rtl/top_templates/neorv32_top_axi4lite.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_top_axi4lite.vhd)
|
|
wrapper the NEORV32 provides an **AXI4-Lite** compatible master interface. This wrapper instantiates the default
|
|
[NEORV32 processor top entitiy](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) and implements a Wishbone to AXI4-Lite bridge.
|
|
|
|
The AXI4-Lite interface has been tested using Xilinx Vivado 19.2 block designer:
|
|
|
|
![AXI-SoC](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_axi_soc.png)
|
|
|
|
The processor was packed as custom IP using `neorv32_top_axi4lite.vhd` as top entity. The AXI interface is automatically detected by the packager.
|
|
All remaining IO interfaces are available as custom signals. The configuration generics are available via the "customize IP" dialog.
|
|
In the figure above the resulting IP block is named "neorv32_top_axi4lite_v1_0".
|
|
*(Note: Use Syntheiss option "global" when generating the block design to maintain the internal TWI tri-state drivers.)*
|
|
|
|
The setup uses an AXI interconnect to attach two block RAMs to the processor. Since the processor in this example is configured *without* IMEM and DMEM,
|
|
the attached block RAMs are used for storing instructions and data: the first RAM is used as instruction memory
|
|
and is mapped to address `0x00000000 - 0x00003fff` (16kB), the second RAM is used as data memory and is mapped to address `0x80000000 - 0x80001fff` (8kB).
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
## Getting Started
|
## Getting Started
|
|
|
This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
|
This overview provides some *quick links* to the most important sections of the :books:
|
|
[NEORV32 online documentation](https://stnolting.github.io/neorv32).
|
[:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
|
|
|
|
|
|
### 0. Build the Documentation
|
|
|
|
This step is optional since there are pre-built versions of the [processor data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
|
|
and the [software documentation](https://stnolting.github.io/neorv32/files.html). If you want to build the documentation by yourself:
|
|
|
|
**NEORV32 Data Sheet**
|
|
|
|
To build the data sheet open a console and navigate to the project's `docs` folder. Run `$ sh make_datasheet.sh` (make sure `asciidoctor-pdf` is installed).
|
|
This will take all the `asciidoc` sources from [`docs/src_adoc`](https://github.com/stnolting/neorv32/blob/master/docs/src_adoc) to generate `docs/NEORV32.pdf`.
|
|
|
|
**Software Framework Documentation**
|
|
|
|
Make sure `doxygen` is installed. Open a console and navigate to the project's `docs` folder and run `$ doxygen Doxyfile`. This will create (if not already there)
|
|
a new folder `docs/doxygen_build/html` where doxygen will generate the HTML-based documentation pages. Open `docs/doxygen_build/html/files.html` to get started.
|
|
|
|
|
|
### 1. Get the Toolchain
|
|
|
|
At first you need a **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
|
|
and build the toolchain by yourself, or you can download a prebuilt one and install it.
|
|
|
|
To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain).
|
|
Make sure to use the `ilp32` or `ilp32e` ABI.
|
|
|
|
**Alternatively**, you can download a prebuilt toolchain. I have uploaded the toolchains I am using to GitHub. These toolchains
|
|
were compiled on a 64-bit x86 Ubuntu 20.04 LTS (Ubuntu on Windows, actually). Download the toolchain of choice:
|
|
[:octocat: github.com/stnolting/riscv-gcc-prebuilt](https://github.com/stnolting/riscv-gcc-prebuilt)
|
|
|
|
You can also use the toolchains provided by [SiFive](https://github.com/sifive/freedom-tools/releases). These are 64-bit toolchains that can also emit 32-bit
|
|
RISC-V code. They were compiled for more sophisticated machines (`rv32imac`) so make sure the according NEORV32 hardware extensions are enabled.
|
|
|
|
:warning: Keep in mind that – for instance – a `rv32imc` toolchain only provides library code compiled with compressed and
|
|
`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
|
|
|
|
To check everything works fine, make sure `GNU Make` and a native `GCC` compiler are installed.
|
|
Test the installation of the RISC-V toolchain by navigating to an [example program project](https://github.com/stnolting/neorv32/tree/master/sw/example) like
|
|
`sw/example/blink_led` and running:
|
|
|
|
neorv32/sw/example/blink_led$ make check
|
|
|
|
|
|
### 2. Download the NEORV32 Project
|
|
|
|
Get the sources of the NEORV32 Processor project. The simplest way is using `git clone` (suggested for easy project updates via `git pull`):
|
|
|
|
$ git clone https://github.com/stnolting/neorv32.git
|
|
|
|
Alternatively, you can either download a specific [release](https://github.com/stnolting/neorv32/releases) or get the most recent version
|
|
of this project as [`*.zip` file](https://github.com/stnolting/neorv32/archive/master.zip).
|
|
|
|
|
|
### 3. Create a new FPGA Project
|
|
|
|
:information_source: If want to use a script-based exemplary project setup check out the [`boards`](https://github.com/stnolting/neorv32/tree/master/boards) folder,
|
|
which provides exemplary setups targeting various FPGA boards.
|
|
|
|
Create a new project with your FPGA design tool of choice. Add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
|
|
folder to this project. Make sure to add these files to a **new design library** called `neorv32`.
|
|
|
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) or one of its
|
|
[wrappers](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) in your own project. If you just want to try thing out,
|
|
you can use the simple [**test setup** (`rtl/top_templates/neorv32_test_setup.vhd`)](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) as top entity.
|
|
|
|
![neorv32 test setup](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_test_setup.png)
|
|
|
|
|
|
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART0 communications lines, clock, reset and some
|
|
GPIO output signals are propagated as actual top entity interface signals. Basically, it is a FPGA version of a "hello world" example:
|
|
|
|
```vhdl
|
|
entity neorv32_test_setup is
|
|
port (
|
|
-- Global control --
|
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
|
-- GPIO --
|
|
gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
|
|
-- UART0 --
|
|
uart0_txd_o : out std_ulogic; -- UART0 send data
|
|
uart0_rxd_i : in std_ulogic := '0' -- UART0 receive data
|
|
);
|
|
end neorv32_test_setup;
|
|
```
|
|
|
|
|
|
### 4. Compile an Example Program
|
|
|
|
The NEORV32 project includes several [example program project](https://github.com/stnolting/neorv32/tree/master/sw/example) from
|
|
which you can start your own application. There are example programs to check out the processor's peripheral like I2C or the true-random number generator.
|
|
And of course there is also a port of [Conway's Game of Life](https://github.com/stnolting/neorv32/tree/master/sw/example/game_of_life) available.
|
|
|
|
Simply compile one of these projects using
|
|
|
|
neorv32/sw/example/blink_led$ make clean_all exe
|
### :electric_plug: Hardware Overview
|
|
|
This will create a NEORV32 *executable* `neorv32_exe.bin` in the same folder, which you can upload via the bootloader.
|
* [NEORV32 Processor](https://stnolting.github.io/neorv32/#_neorv32_processor_soc) - the SoC
|
|
* [Top Entity - Signals](https://stnolting.github.io/neorv32/#_processor_top_entity_signals) - how to connect to the processor
|
|
* [Top Entity - Generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics) - configuration options
|
|
* [Address Space](https://stnolting.github.io/neorv32/#_address_space) - memory space and memory-mapped IO
|
|
* [SoC Modules](https://stnolting.github.io/neorv32/#_processor_internal_modules) - available IO/peripheral modules and memories
|
|
* [On-Chip Debugger](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd) - online debugging of the processor via JTAG
|
|
|
|
* [NEORV32 CPU](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu) - the RISC-V core
|
|
* [RISC-V compatibility](https://stnolting.github.io/neorv32/#_risc_v_compatibility) - what is compatible to the specs. and what is not
|
|
* [ISA and Extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions) - available RISC-V ISA extensions
|
|
* [CSRs](https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs) - control and status registers
|
|
* [Traps](https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts) - interrupts and exceptions
|
|
|
|
### :floppy_disk: Software Overview
|
|
|
|
* [Core Libraries](https://stnolting.github.io/neorv32/#_core_libraries) - high-level functions for accessing the processor's peripherals
|
|
* [Software Framework Documentation](https://stnolting.github.io/neorv32/sw/files.html) - `doxygen`-based documentation
|
|
* [Application Makefiles](https://stnolting.github.io/neorv32/#_application_makefile) - turning your application into an executable
|
|
* [Bootloader](https://stnolting.github.io/neorv32/#_bootloader) - the build-in NEORV32 bootloader
|
|
|
|
### :rocket: User Guides (see [full overview](https://stnolting.github.io/neorv32/#_lets_get_it_started))
|
|
|
|
* [Toolchain Setup](https://stnolting.github.io/neorv32/#_toolchain_setup) - install and setup RISC-V gcc
|
|
* [General Hardware Setup](https://stnolting.github.io/neorv32/#_general_hardware_setup) - setup a new NEORV32 EDA project
|
|
* [General Software Setup](https://stnolting.github.io/neorv32/#_general_software_framework_setup) - configure the software framework
|
|
* [Application Compilation](https://stnolting.github.io/neorv32/#_application_program_compilation) - compile an application using `make`
|
|
* [Upload via Bootloader](https://stnolting.github.io/neorv32/#_uploading_and_starting_of_a_binary_executable_image_via_uart) - upload and execute executables
|
|
* [Debugging via the On-Chip Debugger](https://stnolting.github.io/neorv32/#_debugging_using_the_on_chip_debugger) - step through code *online* and *in-system*
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
### 5. Upload the Executable via the Bootloader
|
|
|
|
Connect your FPGA board via UART to your computer and open the according port to interface with the fancy NEORV32 bootloader. The bootloader
|
|
uses the following default UART configuration:
|
|
|
|
* 19200 Baud
|
|
* 8 data bits
|
|
* 1 stop bit
|
|
* No parity bits
|
|
* No transmission / flow control protocol (raw bytes only)
|
|
* Newline on `\r\n` (carriage return & newline) - also for sent data
|
|
|
|
Use the bootloader console to upload the `neorv32_exe.bin` executable gerated during application compiling and *run* your application.
|
## Acknowledgements
|
|
|
```
|
**A big shoutout to all [contributors](https://github.com/stnolting/neorv32/graphs/contributors), who helped improving this project! :heart:**
|
<< NEORV32 Bootloader >>
|
|
|
|
BLDV: Mar 23 2021
|
[![RISC-V](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/riscv_logo.png)](https://riscv.org/)
|
HWV: 0x01050208
|
|
CLK: 0x05F5E100
|
|
USER: 0x10000DE0
|
|
MISA: 0x40901105
|
|
ZEXT: 0x00000023
|
|
PROC: 0x0EFF0037
|
|
IMEM: 0x00004000 bytes @ 0x00000000
|
|
DMEM: 0x00002000 bytes @ 0x80000000
|
|
|
|
Autoboot in 8s. Press key to abort.
|
[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!
|
Aborted.
|
|
|
|
Available CMDs:
|
Continous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).
|
h: Help
|
|
r: Restart
|
|
u: Upload
|
|
s: Store to flash
|
|
l: Load from flash
|
|
e: Execute
|
|
CMD:> u
|
|
Awaiting neorv32_exe.bin... OK
|
|
CMD:> e
|
|
Booting...
|
|
|
|
Blinking LED demo program
|
![Open Source Hardware Logo https://www.oshwa.org](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/oshw_logo.png)
|
```
|
|
|
|
Going further: Take a look at the _Let's Get It Started!_ chapter of the [:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
## Contribute/Feedback/Questions
|
|
|
|
I'm always thankful for help! So if you have any questions, bug reports, ideas or if you want to give any kind of feedback, feel free
|
|
to [open a new issue](https://github.com/stnolting/neorv32/issues), start a new [discussion on GitHub](https://github.com/stnolting/neorv32/discussions)
|
|
or directly [drop me a line](mailto:stnolting@gmail.com).
|
|
|
|
Here is a simple guide line if you'd like to contribute to this repository:
|
|
|
|
0. :star: this repository :wink:
|
|
1. Check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md)
|
|
2. [Fork](https://github.com/stnolting/neorv32/fork) this repository and clone the fork
|
|
3. Create a feature branch in your fork: `git checkout -b awesome_new_feature_branch`
|
|
4. Create a new remote for the upstream repo: `git remote add upstream https://github.com/stnolting/neorv32`
|
|
5. Commit your modifications: `git commit -m "Awesome new feature!"`
|
|
6. Push to the branch: `git push origin awesome_new_feature_branch`
|
|
7. Create a new [pull request](https://github.com/stnolting/neorv32/pulls)
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
## Legal
|
## Legal
|
|
|
This project is released under the BSD 3-Clause license. No copyright infringement intended.
|
This project is released under the [BSD 3-Clause license](https://github.com/stnolting/neorv32/blob/master/LICENSE).
|
|
No copyright infringement intended.
|
|
For more information see the [online documentation - _"Proprietary and Legal Notice"_](https://stnolting.github.io/neorv32/#_proprietary_and_legal_notice).
|
Other implied or used projects might have different licensing - see their documentation to get more information.
|
Other implied or used projects might have different licensing - see their documentation to get more information.
|
|
|
#### Citing
|
|
|
|
If you are using the NEORV32 or parts of the project in some kind of publication, please cite it as follows:
|
|
|
|
> S. Nolting, "The NEORV32 RISC-V Processor", github.com/stnolting/neorv32
|
|
|
|
#### BSD 3-Clause License
|
|
|
|
Copyright (c) 2021, Stephan Nolting. All rights reserved.
|
|
|
|
Redistribution and use in source and binary forms, with or without modification, are
|
|
permitted provided that the following conditions are met:
|
|
|
|
1. Redistributions of source code must retain the above copyright notice, this list of
|
|
conditions and the following disclaimer.
|
|
2. Redistributions in binary form must reproduce the above copyright notice, this list of
|
|
conditions and the following disclaimer in the documentation and/or other materials
|
|
provided with the distribution.
|
|
3. Neither the name of the copyright holder nor the names of its contributors may be used to
|
|
endorse or promote products derived from this software without specific prior written
|
|
permission.
|
|
|
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
|
|
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
|
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
|
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
|
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
|
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
|
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
|
|
OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
|
|
#### Limitation of Liability for External Links
|
#### Limitation of Liability for External Links
|
|
|
Our website contains links to the websites of third parties ("external links"). As the
|
Our website contains links to the websites of third parties ("external links"). As the
|
content of these websites is not under our control, we cannot assume any liability for
|
content of these websites is not under our control, we cannot assume any liability for
|
such external content. In all cases, the provider of information of the linked websites
|
such external content. In all cases, the provider of information of the linked websites
|
is liable for the content and accuracy of the information provided. At the point in time
|
is liable for the content and accuracy of the information provided. At the point in time
|
when the links were placed, no infringements of the law were recognisable to us. As soon
|
when the links were placed, no infringements of the law were recognisable to us. As soon
|
as an infringement of the law becomes known to us, we will immediately remove the
|
as an infringement of the law becomes known to us, we will immediately remove the
|
link in question.
|
link in question.
|
|
|
|
#### Citing
|
|
|
#### Proprietary Notice
|
If you are using the NEORV32 or parts of the project in some kind of publication, please cite it as follows:
|
|
|
"Artix" and "Vivado" are trademarks of Xilinx Inc.
|
|
|
|
"Cyclone" and "Quartus Prime Lite" are trademarks of Intel Corporation.
|
|
|
|
"iCE40", "UltraPlus" and "Radiant" are trademarks of Lattice Semiconductor Corporation.
|
|
|
|
"AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
|
|
|
|
"NeoPixel" is a trademark of Adafruit Industries.
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
|
## Acknowledgements
|
|
|
|
[![RISC-V](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/riscv_logo.png)](https://riscv.org/)
|
|
|
|
[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!
|
|
|
|
Continous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).
|
|
|
|
![Open Source Hardware Logo https://www.oshwa.org](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/oshw_logo.png)
|
|
|
|
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
|
> S. Nolting, "The NEORV32 RISC-V Processor", github.com/stnolting/neorv32
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
--------
|
--------
|
|
|