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[](https://stnolting.github.io/neorv32)
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[](https://stnolting.github.io/neorv32)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AImplementation)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AImplementation)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AWindows)
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[](https://github.com/stnolting/neorv32)
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[](https://github.com/stnolting/neorv32)
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# The NEORV32 RISC-V Processor
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# The NEORV32 RISC-V Processor
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU.
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU.
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The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone
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The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone
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custom / customizable microcontroller.
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custom / customizable microcontroller.
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:information_source: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
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:books: For detailed information take a look at the [NEORV32 documentation (online at GitHub-pages)](https://stnolting.github.io/neorv32/).
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:books: For detailed information take a look at the [NEORV32 documentation (online at GitHub-pages)](https://stnolting.github.io/neorv32/).
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The *doxygen*-based documentation of the *software framework* is also available online
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The *doxygen*-based documentation of the *software framework* is also available online
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at [GitHub-pages](https://stnolting.github.io/neorv32/sw/files.html).
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at [GitHub-pages](https://stnolting.github.io/neorv32/sw/files.html).
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:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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To see the changes between *official* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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To see the changes between *official* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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:package: The [`boards`](https://github.com/stnolting/neorv32/tree/master/boards) folder provides exemplary EDA setups targeting
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:package: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary setups targeting
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various FPGA boards to get you started.
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various FPGA boards and toolchains to get you started.
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:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
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:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
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**TODOs**, features being **planned** and **work-in-progress**.
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**TODOs**, features being **planned** and **work-in-progress**.
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:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
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:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
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**SoC Connectivity and Integration**
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**SoC Connectivity and Integration**
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* 32-bit external bus interface, Wishbone b4 compatible
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* 32-bit external bus interface, Wishbone b4 compatible
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([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
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([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
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* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_top_axi4lite.vhd) for AXI4-Lite master interface
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* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/templates/system/neorv32_SystemTop_axi4lite.vhd) for AXI4-Lite master interface
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* alternative [top entities/wrappers](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) providing
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* 32-bit stram link interface with up to 8 independent RX and TX links
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simplified and/or resolved top entity ports for easy system inegration
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([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))
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* AXI4-Stream compatible
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* external interrupt controller with up to 32 channels
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([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
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* alternative [top entities/wrappers](https://github.com/stnolting/neorv32/blob/master/rtl/templates) providing
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simplified and/or resolved top entity ports for easy system integration
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* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
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* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
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for tightly-coupled custom co-processor extensions
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for tightly-coupled custom co-processor extensions
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**Advanced**
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**Advanced**
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* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
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* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
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* numerically-controlled oscillator ([NCO](https://stnolting.github.io/neorv32/#_numerically_controlled_oscillator_nco))
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* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) via JTGA - implementing
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* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) via JTGA - implementing
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the [*Minimal RISC-V Debug Specification Version 0.13.2*](https://github.com/riscv/riscv-debug-spec)
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the [*Minimal RISC-V Debug Specification Version 0.13.2*](https://github.com/riscv/riscv-debug-spec)
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and compatible with the *OpenOCD* and *gdb*
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and compatible with *OpenOCD* and *gdb*
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:information_source: It is recommended to use the processor setup even if you want to **use the CPU in stand-alone mode**.
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:information_source: It is recommended to use the processor setup even if you want to **use the CPU in stand-alone mode**. Simply disable all the processor-internal
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Just disable all optional processor-internal modules via the according generics and you will get a "CPU wrapper" that
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modules via the generics and you will get a "CPU wrapper" that already provides a minimal CPU environment and an external memory interface (like AXI4).
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provides a minimal CPU environment and an external memory interface (like AXI4). This minimal setup allows to further use
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This setup also allows to further use the default bootloader and software framework. From this base you can start building your own processor system.
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the default bootloader and software framework. From this base you can start building your own processor system.
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### FPGA Implementation Results - Processor
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### FPGA Implementation Results - Processor
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:information_source: Check out the [`boards`](https://github.com/stnolting/neorv32/tree/master/boards)
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The hardware resources used by a specifc processor setup is defined by the implemented CPU extensions
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folder for exemplary setups targeting various FPGA boards.
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([see below](#FPGA-Implementation-Results---CPU)), the configuration of the peripheral modules and some "glue logic".
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Section [_"Processor Modules"_](https://stnolting.github.io/neorv32/#_processor_modules) of the online datasheet shows
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:information_source: The hardware resources used by the processor-internal IO/peripheral modules andmemories is also available in the
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the ressource utilization of each optional processor module to estimate the actual setup's hardware requirements.
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[online documentation - _"NEORV32 Central Processing Unit"_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu).
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:information_source: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary FPGA
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Results generated for hardware version [`1.4.9.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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setups targeting various FPGA boards and toolchains. These setups also provide ressource utilization reports for different
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If not otherwise note, the setups use *the default configuration* (like no *TRNG*),
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SoC configurations
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no external memory interface and only internal instruction and data memories
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(IMEM uses 16kB and DMEM uses 8kB memory space).
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| Vendor | FPGA | Board | Toolchain | CPU Configuration | LUT / LE | FF / REG | DSP (9-bit) | Memory Bits | BRAM / EBR | SPRAM | Frequency |
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|:--------|:----------------------------------|:-----------------|:---------------------------|:----------------------------------|:-----------|:-----------|:------------|:-------------|:-----------|:---------|--------------:|
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| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 20.1 | `rv32imcu_Zicsr_Zifencei` | 3813 (17%) | 1904 (8%) | 0 (0%) | 231424 (38%) | - | - | 119 MHz |
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| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | [`boards/UPduino_v3`](https://github.com/stnolting/neorv32/tree/master/boards/UPduino_v3) | Radiant 2.1 (LSE) | `rv32imac_Zicsr` | 5123 (97%) | 1972 (37%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 24 MHz |
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| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | `rv32imcu_Zicsr_Zifencei` + `PMP` | 2465 (12%) | 1912 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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:books: In-depth detailed information regarding the CPU can be found in the
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:books: In-depth detailed information regarding the CPU can be found in the
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[online documentation - _"NEORV32 Central Processing Unit"_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu).
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[online documentation - _"NEORV32 Central Processing Unit"_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu).
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The CPU (top entity: [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd))
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The CPU (top entity: [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd))
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implements the RISC-V 32-bit `rv32` ISA with optional extensions. It is compatible to a subset of the
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implements the RISC-V 32-bit `rv32` ISA with optional extensions (see below). It is compatible to a subset of the
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*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
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*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
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and a subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
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and a subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
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The CPU _passes_ the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test)
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Compatiility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test)
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(see [`riscv-arch-test/README`](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md)).
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(see [`riscv-arch-test/README`](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md)).
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NEORV32 is an official (see [architecture ID](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)) little-endian
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The core implements a little-endian von-Neumann architecture using two pipeline stages. Each stage uses a multi-cycle processing
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two-stage (+ multi-cycle) RISC-V CPU with independent instruction/data bus interfaces, and multiple supported operating
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scheme. The CPU supports three privilege levels (`machine` and optional `user` and `debug_mode`), three standard RISC-V machine
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modes / privilege levels: `machine` and optional `user` and `debug_mode`.
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interrupts (`MTI`, `MEI`, `MSI`), a single non-maskable interrupt plus 16 _fast interrupt requests_ as custom extensions.
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It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
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It supports the _standard_ RISC-V machine interrupts (`MTI`, `MEI`, `MSI`) and 1 non-maskable interrupt as well as 16
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instruction, breakpoint, environment call). As a special "execution safety" extension, _all_ invalid, reserved or
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_fast interrupt requests_ as custom extensions. The CPU also supports **all** standard RISC-V exceptions
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malformed instructions will raise an exception.
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(instruction/load/store misaligned address & bus access fault, illegal instruction, breakpoint, environment call).
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As a special "execution safety" extension, _all_ invalid, reserved or malformed instructions will raise an illegal
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instruction exception.
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### Available ISA Extensions
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### Available ISA Extensions
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Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
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Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
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[[`U`](https://stnolting.github.io/neorv32/#_u_less_privileged_user_mode)]
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[[`U`](https://stnolting.github.io/neorv32/#_u_less_privileged_user_mode)]
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[[`X`](https://stnolting.github.io/neorv32/#_x_neorv32_specific_custom_extensions)]
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[[`X`](https://stnolting.github.io/neorv32/#_x_neorv32_specific_custom_extensions)]
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[[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_single_precision_floating_point_operations)]
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[[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_single_precision_floating_point_operations)]
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[[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_control_and_status_register_access_privileged_architecture)]
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[[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_control_and_status_register_access_privileged_architecture)]
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[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
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[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
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[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_integer_multiplication)]
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[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
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[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
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[[`HPM`](https://stnolting.github.io/neorv32/#_hpm_hardware_performance_monitors)]**
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[[`HPM`](https://stnolting.github.io/neorv32/#_hpm_hardware_performance_monitors)]**
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:information_source: The `B` ISA extension has been temporarily removed from the processor.
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:information_source: The `B` ISA extension has been temporarily removed from the processor.
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See [B ISA Extension](https://github.com/stnolting/neorv32/projects/7) project board.
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See [B ISA Extension](https://github.com/stnolting/neorv32/projects/7) project board.
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### FPGA Implementation Results - CPU
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### FPGA Implementation Results - CPU
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:books: More details regarding exemplary FPGA setups including a listing of resource utilization by each SoC module can be found in the
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:books: More details regarding exemplary FPGA setups including a list of resource utilization by each SoC module can be found in the
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[online documentation - _"FPGA Implementation Results"_](https://stnolting.github.io/neorv32/#_fpga_implementation_results).
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[online documentation - _"FPGA Implementation Results"_](https://stnolting.github.io/neorv32/#_fpga_implementation_results).
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Implementation results for exemplary CPU configuration generated for an **Intel Cyclone IV EP4CE22F17C6N FPGA**
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Implementation results for exemplary CPU configuration generated for an **Intel Cyclone IV EP4CE22F17C6N FPGA**
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using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing information is derived
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using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing information is derived
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from the Timing Analyzer / Slow 1200mV 0C Model. No constraints were used at all.
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from the Timing Analyzer / Slow 1200mV 0C Model. No constraints were used at all.
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Results generated for hardware version [`1.5.3.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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Results generated for hardware version [`1.5.3.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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| CPU Configuration | LEs | FFs | Memory bits | DSPs (9-bit) | f_max |
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| CPU Configuration | LEs | FFs | Memory bits | DSPs (9-bit) | f_max |
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|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
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|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
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| `rv32i` | 980 | 409 | 1024 | 0 | 123 MHz |
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| `rv32i` | 980 | 409 | 1024 | 0 | 125 MHz |
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| `rv32i` + `Zicsr` | 1835 | 856 | 1024 | 0 | 124 MHz |
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| `rv32i` + `Zicsr` | 1835 | 856 | 1024 | 0 | 125 MHz |
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| `rv32imac` + `Zicsr` | 2685 | 1156 | 1024 | 0 | 124 MHz |
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| `rv32imac` + `Zicsr` | 2685 | 1156 | 1024 | 0 | 125 MHz |
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| `rv32imac` + `Zicsr` + `u` + `Zifencei` + `Zfinx` | 4004 | 1812 | 1024 | 7 | 121 MHz |
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| `rv32imac` + `Zicsr` + `u` + `Zifencei` + `Zfinx` | 4004 | 1812 | 1024 | 7 | 118 MHz |
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### Performance
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### Performance
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The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme.
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The NEORV32 CPU is based on a two-stages pipelined architecutre. Since both stage use a multi-cycle processing scheme,
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Hence, each instruction requires several clock cycles to execute (2 cycles for ALU operations, and up to 40 cycles for divisions).
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each instruction requires several clock cycles to execute (2 cycles for ALU operations, up to 40 cycles for divisions).
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*By default* the CPU-internal shifter as well as the multiplier and divider of the `M` extension use a bit-serial approach
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The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
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and require several cycles for completion. The average CPI (cycles per instruction) depends on the instruction mix of a
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available CPU extensions.
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specific applications and also on the available CPU extensions.
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The following table shows the performance results(relative CoreMark score and average cycles per instruction) for successfully
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The following table shows the performance results(relative CoreMark score and average cycles per instruction) for successfully
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running 2000 iterations of the [CoreMark CPU benchmark](https://www.eembc.org/coremark), which reflects a pretty good "real-life" work load.
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running 2000 iterations of the [CoreMark CPU benchmark](https://www.eembc.org/coremark).
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The source files are available in [sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark).
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The source files are available in [sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark).
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~~~
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~~~
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**CoreMark Setup**
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**CoreMark Setup**
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Hardware: 32kB IMEM, 8kB DMEM, no caches, 100MHz clock
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Hardware: 32kB IMEM, 8kB DMEM, no caches, 100MHz clock
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[online Data Sheet](https://stnolting.github.io/neorv32) and the
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[online Data Sheet](https://stnolting.github.io/neorv32) and the
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[online User Guide](https://stnolting.github.io/neorv32/ug).
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[online User Guide](https://stnolting.github.io/neorv32/ug).
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### :electric_plug: Hardware Overview
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### :electric_plug: Hardware Overview
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* [Rationale](https://stnolting.github.io/neorv32/#_rationale) - NEORV32: why, how come, what for
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* [NEORV32 Processor](https://stnolting.github.io/neorv32/#_neorv32_processor_soc) - the SoC
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* [NEORV32 Processor](https://stnolting.github.io/neorv32/#_neorv32_processor_soc) - the SoC
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* [Top Entity - Signals](https://stnolting.github.io/neorv32/#_processor_top_entity_signals) - how to connect to the processor
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* [Top Entity - Signals](https://stnolting.github.io/neorv32/#_processor_top_entity_signals) - how to connect to the processor
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* [Top Entity - Generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics) - configuration options
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* [Top Entity - Generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics) - configuration options
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* [Address Space](https://stnolting.github.io/neorv32/#_address_space) - memory space and memory-mapped IO
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* [Address Space](https://stnolting.github.io/neorv32/#_address_space) - memory layout and boot configuration
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* [SoC Modules](https://stnolting.github.io/neorv32/#_processor_internal_modules) - available IO/peripheral modules and memories
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* [SoC Modules](https://stnolting.github.io/neorv32/#_processor_internal_modules) - available IO/peripheral modules and memories
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* [On-Chip Debugger](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd) - online debugging of the processor via JTAG
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* [On-Chip Debugger](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd) - online & in-system debugging of the processor via JTAG
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* [NEORV32 CPU](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu) - the RISC-V core
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* [NEORV32 CPU](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu) - the RISC-V core
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* [RISC-V compatibility](https://stnolting.github.io/neorv32/#_risc_v_compatibility) - what is compatible to the specs. and what is not
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* [RISC-V compatibility](https://stnolting.github.io/neorv32/#_risc_v_compatibility) - what is compatible to the specs. and what is not
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* [ISA and Extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions) - available RISC-V ISA extensions
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* [ISA and Extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions) - available RISC-V ISA extensions
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* [CSRs](https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs) - control and status registers
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* [CSRs](https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs) - control and status registers
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* [Debugging via the On-Chip Debugger](https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger) - step through code *online* and *in-system*
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* [Debugging via the On-Chip Debugger](https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger) - step through code *online* and *in-system*
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### :copyright: Legal
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### :copyright: Legal
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* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, proprietary notice, ...
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* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, proprietary notice, ...
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* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information
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* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information (DOI)
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* [Impressum](https://github.com/stnolting/neorv32/blob/master/docs/impressum.md) - imprint (:de:)
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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