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[](https://stnolting.github.io/neorv32)
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[](https://stnolting.github.io/neorv32)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
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\
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AImplementation)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AImplementation)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AWindows)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AWindows)
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# The NEORV32 RISC-V Processor
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# The NEORV32 RISC-V Processor
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://doi.org/10.5281/zenodo.5121427)
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://stnolting.github.io/neorv32)
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[](https://stnolting.github.io/neorv32)
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://stnolting.github.io/neorv32/ug)
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[](https://stnolting.github.io/neorv32/ug)
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[](https://stnolting.github.io/neorv32/sw/files.html)
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[](https://stnolting.github.io/neorv32/sw/files.html)
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:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
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:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
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**TODOs**, features being **planned** and **work-in-progress**.
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**TODOs**, features being **planned** and **work-in-progress**.
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:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
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:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
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[new discussion](https://github.com/stnolting/neorv32/discussions) if you have questions, comments, ideas or bug-fixes.
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[new discussion](https://github.com/stnolting/neorv32/discussions) if you have questions, comments, ideas or if something is
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not working as expected.
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Check out how to contribute in [`CONTRIBUTE.md`](https://github.com/stnolting/neorv32/blob/master/CONTRIBUTING.md).
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Check out how to contribute in [`CONTRIBUTE.md`](https://github.com/stnolting/neorv32/blob/master/CONTRIBUTING.md).
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:rocket: Check out the [quick links below](#Getting-Started) or directly jump to the
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:rocket: Check out the [quick links below](#Getting-Started) or directly jump to the
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[*User Guide*](https://stnolting.github.io/neorv32/ug/) to get started
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[*User Guide*](https://stnolting.github.io/neorv32/ug/) to get started
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setting up your NEORV32 setup!
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setting up your NEORV32 setup!
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### FPGA Implementation Results - Processor
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### FPGA Implementation Results - Processor
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The hardware resources used by a specifc processor setup is defined by the implemented CPU extensions
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The hardware resources used by a specifc processor setup is defined by the implemented CPU extensions
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([see below](#FPGA-Implementation-Results---CPU)), the configuration of the peripheral modules and some "glue logic".
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([see below](#FPGA-Implementation-Results---CPU)), the configuration of the peripheral modules and some "glue logic".
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Section [_"Processor Modules"_](https://stnolting.github.io/neorv32/#_processor_modules) of the online datasheet shows
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Section [_"FPGA Implementation Results - Processor Modules"_](https://stnolting.github.io/neorv32/#_processor_modules)
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the ressource utilization of each optional processor module to estimate the actual setup's hardware requirements.
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of the online datasheet shows the ressource utilization of each optional processor module to allow an
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estimation of the actual setup's hardware requirements.
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:information_source: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary FPGA
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:information_source: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary FPGA
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setups targeting various FPGA boards and toolchains. These setups also provide ressource utilization reports for different
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setups targeting various FPGA boards and toolchains. These setups also provide ressource utilization reports for different
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SoC configurations
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SoC configurations
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The CPU (top entity: [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd))
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The CPU (top entity: [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd))
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implements the RISC-V 32-bit `rv32` ISA with optional extensions (see below). It is compatible to a subset of the
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implements the RISC-V 32-bit `rv32` ISA with optional extensions (see below). It is compatible to a subset of the
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*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
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*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
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and a subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
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and a subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
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Compatiility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test)
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Compatiility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test)
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(see [`riscv-arch-test/README`](https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/README.md)).
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(see [`sim/README`](sim/README.md)).
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The core implements a little-endian von-Neumann architecture using two pipeline stages. Each stage uses a multi-cycle processing
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The core implements a little-endian von-Neumann architecture using two pipeline stages. Each stage uses a multi-cycle processing
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scheme. The CPU supports three privilege levels (`machine` and optional `user` and `debug_mode`), three standard RISC-V machine
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scheme. The CPU supports three privilege levels (`machine` and optional `user` and `debug_mode`), three standard RISC-V machine
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interrupts (`MTI`, `MEI`, `MSI`), a single non-maskable interrupt plus 16 _fast interrupt requests_ as custom extensions.
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interrupts (`MTI`, `MEI`, `MSI`), a single non-maskable interrupt plus 16 _fast interrupt requests_ as custom extensions.
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It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
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It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
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instruction, breakpoint, environment call). As a special "execution safety" extension, _all_ invalid, reserved or
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instruction, breakpoint, environment call)
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malformed instructions will raise an exception.
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(see :books: [_"Full Virtualization"_](https://stnolting.github.io/neorv32/#_full_virtualization)).
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### Available ISA Extensions
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### Available ISA Extensions
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Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
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Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### FPGA Implementation Results - CPU
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### FPGA Implementation Results - CPU
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:books: More details regarding exemplary FPGA setups including a list of resource utilization by each SoC module can be found in the
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Implementation results for _exemplary_ CPU configuration generated for an **Intel Cyclone IV EP4CE22F17C6N FPGA**
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[online documentation - _"FPGA Implementation Results"_](https://stnolting.github.io/neorv32/#_fpga_implementation_results).
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Implementation results for exemplary CPU configuration generated for an **Intel Cyclone IV EP4CE22F17C6N FPGA**
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using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing information is derived
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using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing information is derived
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from the Timing Analyzer / Slow 1200mV 0C Model. No constraints were used at all.
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from the Timing Analyzer / Slow 1200mV 0C Model. No constraints were used at all.
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Results generated for hardware version [`1.5.3.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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Results generated for hardware version [`1.5.7.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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| CPU Configuration | LEs | FFs | Memory bits | DSPs (9-bit) | f_max |
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| CPU Configuration | LEs | FFs | Memory bits | DSPs (9-bit) | f_max |
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|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
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|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
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| `rv32i` | 980 | 409 | 1024 | 0 | 125 MHz |
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| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
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| `rv32i` + `Zicsr` | 1835 | 856 | 1024 | 0 | 125 MHz |
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| `rv32i_Zicsr` | 1729 | 813 | 1024 | 0 | 124 MHz |
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| `rv32imac` + `Zicsr` | 2685 | 1156 | 1024 | 0 | 125 MHz |
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| `rv32imac_Zicsr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
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| `rv32imac` + `Zicsr` + `u` + `Zifencei` + `Zfinx` | 4004 | 1812 | 1024 | 7 | 118 MHz |
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:information_source: An incrmental list of CPU exntension's hardware utilization can found in
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[online documentation - _"FPGA Implementation Results - CPU"_](https://stnolting.github.io/neorv32/#_cpu).
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:information_source: The CPU provides options to further reduce the footprint (for example by constraining
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the CPU-internal counters). See the [online data](https://stnolting.github.io/neorv32) sheet for more information.
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### Performance
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### Performance
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The NEORV32 CPU is based on a two-stages pipelined architecutre. Since both stage use a multi-cycle processing scheme,
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The NEORV32 CPU is based on a two-stages pipelined architecutre. Since both stage use a multi-cycle processing scheme,
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each instruction requires several clock cycles to execute (2 cycles for ALU operations, up to 40 cycles for divisions).
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each instruction requires several clock cycles to execute (2 cycles for ALU operations, up to 40 cycles for divisions).
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The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
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The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
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available CPU extensions.
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available CPU extensions.
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The following table shows the performance results(relative CoreMark score and average cycles per instruction) for successfully
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The following table shows the performance results (relative CoreMark score and average cycles per instruction) for
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running 2000 iterations of the [CoreMark CPU benchmark](https://www.eembc.org/coremark).
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_exemplary_ CPU configuration running 2000 iterations of the [CoreMark CPU benchmark](https://www.eembc.org/coremark).
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The source files are available in [sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark).
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The source files are available in [`sw/example/coremark`](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark).
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~~~
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~~~
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**CoreMark Setup**
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**CoreMark Setup**
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Hardware: 32kB IMEM, 8kB DMEM, no caches, 100MHz clock
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Hardware: 32kB IMEM, 8kB DMEM, no caches, 100MHz clock
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CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
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CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
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Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
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Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
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Compiler flags: default, see makefile; optimization -O3
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Compiler flags: default, see makefile; optimization -O3
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~~~
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~~~
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Results generated for hardware version [`1.4.9.8`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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Results generated for hardware version [`1.5.7.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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| CPU (including `Zicsr` extension) | Executable Size | CoreMark Score | CoreMarks/MHz | Total Clock Cycles | Executed Instructions | Average CPI |
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| CPU Configuration | CoreMark Score | CoreMarks/MHz | Average CPI |
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|:--------------------------------------------|:---------------:|:--------------:|:-------------:|-------------------:|----------------------:|:-----------:|
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|:-----------------------------------------------|:--------------:|:-------------:|:-----------:|
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| `rv32i` | 28 756 bytes | 36.36 | **0.3636** | 5595750503 | 1466028607 | **3.82** |
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| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04** |
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| `rv32imc` | 22 008 bytes | 68.97 | **0.6897** | 2981786734 | 611814918 | **4.87** |
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| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34** |
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| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 22 008 bytes | 90.91 | **0.9091** | 2265135174 | 611814948 | **3.70** |
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| _performance_(`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54** |
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:information_source: The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension.
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:information_source: More information regarding the CPU performance can be found in the
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The `FAST_SHIFT_EN` configuration uses a barrel shifter for CPU shift operations.
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[online documentation - _"CPU Performance"_](https://stnolting.github.io/neorv32/#_cpu_performance).
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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