| Line 48... |
Line 48... |
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:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
To see the changes between *official* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
|
To see the changes between *official* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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|
|
:package: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary setups targeting
|
:package: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary setups targeting
|
various FPGA boards and toolchains to get you started.
|
various FPGA boards and toolchains to get you started. Several example programs to be run on your setup can be found in
|
|
[`sw/example`](https://github.com/stnolting/neorv32/tree/master/sw/example).
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|
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:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
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:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
|
**TODOs**, features being **planned** and **work-in-progress**.
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**TODOs**, features being **planned** and **work-in-progress**.
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:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
|
:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
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| Line 112... |
Line 113... |
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**SoC Connectivity and Integration**
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**SoC Connectivity and Integration**
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* 32-bit external bus interface, Wishbone b4 compatible
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* 32-bit external bus interface, Wishbone b4 compatible
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([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
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([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
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* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/templates/system/neorv32_SystemTop_axi4lite.vhd) for AXI4-Lite master interface
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* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd) for AXI4-Lite master interface
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* 32-bit stram link interface with up to 8 independent RX and TX links
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* 32-bit stram link interface with up to 8 independent RX and TX links
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([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))
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([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))
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* AXI4-Stream compatible
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* AXI4-Stream compatible
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* external interrupt controller with up to 32 channels
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* external interrupt controller with up to 32 channels
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([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
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([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
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* alternative [top entities/wrappers](https://github.com/stnolting/neorv32/blob/master/rtl/templates) providing
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simplified and/or resolved top entity ports for easy system integration
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* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
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* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
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for tightly-coupled custom co-processor extensions
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for tightly-coupled custom co-processor extensions
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**Advanced**
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**Advanced**
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| Line 187... |
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[[`A`](https://stnolting.github.io/neorv32/#_a_atomic_memory_access)]
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[[`A`](https://stnolting.github.io/neorv32/#_a_atomic_memory_access)]
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[[`C`](https://stnolting.github.io/neorv32/#_c_compressed_instructions)]
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[[`C`](https://stnolting.github.io/neorv32/#_c_compressed_instructions)]
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[[`M`](https://stnolting.github.io/neorv32/#_m_integer_multiplication_and_division)]
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[[`M`](https://stnolting.github.io/neorv32/#_m_integer_multiplication_and_division)]
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[[`U`](https://stnolting.github.io/neorv32/#_u_less_privileged_user_mode)]
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[[`U`](https://stnolting.github.io/neorv32/#_u_less_privileged_user_mode)]
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[[`X`](https://stnolting.github.io/neorv32/#_x_neorv32_specific_custom_extensions)]
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[[`X`](https://stnolting.github.io/neorv32/#_x_neorv32_specific_custom_extensions)]
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[[`Zbb`](https://stnolting.github.io/neorv32/#_zbb_basic_bit_manipulation_operations)]
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[[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_single_precision_floating_point_operations)]
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[[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_single_precision_floating_point_operations)]
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[[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_control_and_status_register_access_privileged_architecture)]
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[[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_control_and_status_register_access_privileged_architecture)]
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[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
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[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
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[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_integer_multiplication)]
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[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_integer_multiplication)]
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[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
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[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
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[[`HPM`](https://stnolting.github.io/neorv32/#_hpm_hardware_performance_monitors)]**
|
[[`HPM`](https://stnolting.github.io/neorv32/#_hpm_hardware_performance_monitors)]
|
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[[`DEBUG`](https://stnolting.github.io/neorv32/#_cpu_debug_mode)]**
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|
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:information_source: The `B` ISA extension has been temporarily removed from the processor.
|
:warning: The `Zbb`, `Zfinx` and `Zmmul` RISC-V extensions are frozen but not officially ratified yet. Hence, there is no
|
See [B ISA Extension](https://github.com/stnolting/neorv32/projects/7) project board.
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upstream gcc support. To circumvence this, the NEORV32 software framework provides _intrinsic_ libraries for these extensions.
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|
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### FPGA Implementation Results - CPU
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### FPGA Implementation Results - CPU
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| Line 214... |
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|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
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|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
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| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
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| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
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| `rv32i_Zicsr` | 1729 | 813 | 1024 | 0 | 124 MHz |
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| `rv32i_Zicsr` | 1729 | 813 | 1024 | 0 | 124 MHz |
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| `rv32imac_Zicsr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
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| `rv32imac_Zicsr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
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|
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:information_source: An incrmental list of CPU exntension's hardware utilization can found in
|
:information_source: An incremental list of CPU exntension's hardware utilization can found in
|
[online documentation - _"FPGA Implementation Results - CPU"_](https://stnolting.github.io/neorv32/#_cpu).
|
[online documentation - _"FPGA Implementation Results - CPU"_](https://stnolting.github.io/neorv32/#_cpu).
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|
|
:information_source: The CPU provides options to further reduce the footprint (for example by constraining
|
:information_source: The CPU provides options to further reduce the footprint (for example by constraining
|
the CPU-internal counters). See the [online data](https://stnolting.github.io/neorv32) sheet for more information.
|
the CPU-internal counters). See the [online data](https://stnolting.github.io/neorv32) sheet for more information.
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| Line 234... |
Line 235... |
|
|
The following table shows the performance results (relative CoreMark score and average cycles per instruction) for
|
The following table shows the performance results (relative CoreMark score and average cycles per instruction) for
|
_exemplary_ CPU configuration running 2000 iterations of the [CoreMark CPU benchmark](https://www.eembc.org/coremark).
|
_exemplary_ CPU configuration running 2000 iterations of the [CoreMark CPU benchmark](https://www.eembc.org/coremark).
|
The source files are available in [`sw/example/coremark`](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark).
|
The source files are available in [`sw/example/coremark`](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark).
|
|
|
|
:information_source: A _simple_ port of the **Dhrystone** benchmark is also available:
|
|
[`sw/example/dhrystone`](https://github.com/stnolting/neorv32/blob/master/sw/example/dhrystone)
|
|
|
~~~
|
~~~
|
**CoreMark Setup**
|
**CoreMark Setup**
|
Hardware: 32kB IMEM, 8kB DMEM, no caches, 100MHz clock
|
Hardware: 32kB IMEM, 8kB DMEM, no caches, 100MHz clock
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
| Line 298... |
Line 302... |
* [Top Entity - Generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics) - configuration options
|
* [Top Entity - Generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics) - configuration options
|
* [Address Space](https://stnolting.github.io/neorv32/#_address_space) - memory layout and boot configuration
|
* [Address Space](https://stnolting.github.io/neorv32/#_address_space) - memory layout and boot configuration
|
* [SoC Modules](https://stnolting.github.io/neorv32/#_processor_internal_modules) - available IO/peripheral modules and memories
|
* [SoC Modules](https://stnolting.github.io/neorv32/#_processor_internal_modules) - available IO/peripheral modules and memories
|
* [On-Chip Debugger](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd) - online & in-system debugging of the processor via JTAG
|
* [On-Chip Debugger](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd) - online & in-system debugging of the processor via JTAG
|
|
|
* [NEORV32 CPU](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu) - the RISC-V core
|
* [NEORV32 CPU](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu) - the CPU
|
* [RISC-V compatibility](https://stnolting.github.io/neorv32/#_risc_v_compatibility) - what is compatible to the specs. and what is not
|
* [RISC-V compatibility](https://stnolting.github.io/neorv32/#_risc_v_compatibility) - what is compatible to the specs. and what is not
|
* [ISA and Extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions) - available RISC-V ISA extensions
|
* [ISA and Extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions) - available RISC-V ISA extensions
|
* [CSRs](https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs) - control and status registers
|
* [CSRs](https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs) - control and status registers
|
* [Traps](https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts) - interrupts and exceptions
|
* [Traps](https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts) - interrupts and exceptions
|
|
|
| Line 318... |
Line 322... |
* [Toolchain Setup](https://stnolting.github.io/neorv32/ug/#_toolchain_setup) - install and setup RISC-V gcc
|
* [Toolchain Setup](https://stnolting.github.io/neorv32/ug/#_toolchain_setup) - install and setup RISC-V gcc
|
* [General Hardware Setup](https://stnolting.github.io/neorv32/ug/#_general_hardware_setup) - setup a new NEORV32 EDA project
|
* [General Hardware Setup](https://stnolting.github.io/neorv32/ug/#_general_hardware_setup) - setup a new NEORV32 EDA project
|
* [General Software Setup](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup) - configure the software framework
|
* [General Software Setup](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup) - configure the software framework
|
* [Application Compilation](https://stnolting.github.io/neorv32/ug/#_application_program_compilation) - compile an application using `make`
|
* [Application Compilation](https://stnolting.github.io/neorv32/ug/#_application_program_compilation) - compile an application using `make`
|
* [Upload via Bootloader](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart) - upload and execute executables
|
* [Upload via Bootloader](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart) - upload and execute executables
|
|
* [Application-Specific Processor Configuration](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration) - tailor the processor to your needs
|
* [Debugging via the On-Chip Debugger](https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger) - step through code *online* and *in-system*
|
* [Debugging via the On-Chip Debugger](https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger) - step through code *online* and *in-system*
|
|
* [Simulation](https://stnolting.github.io/neorv32/ug/#_simulating_the_processor) - simulate the whole SoC
|
|
* [Hello World!](https://stnolting.github.io/neorv32/ug/index.html#_hello_world) - run a quick _"hello world"_ simulation
|
|
|
### :copyright: Legal
|
### :copyright: Legal
|
|
|
* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, proprietary notice, ...
|
* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, proprietary notice, ...
|
* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information (DOI)
|
* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information (DOI)
|
