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[](https://stnolting.github.io/neorv32)
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[](https://stnolting.github.io/neorv32)
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://stnolting.github.io/neorv32/ug)
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[](https://stnolting.github.io/neorv32/ug)
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[](https://stnolting.github.io/neorv32/sw/files.html)
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[](https://stnolting.github.io/neorv32/sw/files.html)
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|
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* [Overview](#Overview)
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1. [Overview](#1-Overview)
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* [Processor/SoC Features](#NEORV32-Processor-Features)
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1. [Key Features](#Project-Key-Features)
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* [FPGA Implementation Results](#FPGA-Implementation-Results---Processor)
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2. [Processor/SoC Features](#2-NEORV32-Processor-Features)
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* [CPU Features](#NEORV32-CPU-Features)
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1. [FPGA Implementation Results](#FPGA-Implementation-Results---Processor)
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* [Available ISA Extensions](#Available-ISA-Extensions)
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3. [CPU Features](#3-NEORV32-CPU-Features)
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* [FPGA Implementation Results](#FPGA-Implementation-Results---CPU)
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1. [Available ISA Extensions](#Available-ISA-Extensions)
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* [Performance](#Performance)
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2. [FPGA Implementation Results](#FPGA-Implementation-Results---CPU)
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* [Software Framework & Tooling](#Software-Framework-and-Tooling)
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3. [Performance](#Performance)
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* [**Getting Started**](#Getting-Started) :rocket:
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4. [Software Framework & Tooling](#4-Software-Framework-and-Tooling)
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5. [**Getting Started**](#5-Getting-Started) :rocket:
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## Overview
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## 1. Overview
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU.
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU.
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The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone
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The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone
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setting up your NEORV32 setup!
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setting up your NEORV32 setup!
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### Project Key Features
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### Project Key Features
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* [CPU](#NEORV32-CPU-Features) plus [Processor/SoC](#NEORV32-Processor-Features) plus [Software Framework & Tooling](#Software-Framework-and-Tooling)
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- [x] all-in-one: [CPU](#NEORV32-CPU-Features) plus [Processor/SoC](#NEORV32-Processor-Features) plus [Software Framework & Tooling](#Software-Framework-and-Tooling)
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* completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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- [x] completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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* fully synchronous design, no latches, no gated clocks
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- [x] fully synchronous design, no latches, no gated clocks
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* be as small as possible (while being as RISC-V-compliant as possible) – but with a reasonable size-performance trade-off
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- [x] be as small as possible (while being as RISC-V-compliant as possible) – but with a reasonable size-performance trade-off
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(the processor has to fit in a Lattice iCE40 UltraPlus 5k low-power FPGA running at 22+ MHz)
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(the processor has to fit in a Lattice iCE40 UltraPlus 5k low-power FPGA running at 22+ MHz)
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* from zero to `printf("hello world!");` - completely open source and documented
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- [x] from zero to `printf("hello world!");` - completely open source and documented
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* easy to use even for FPGA/RISC-V starters – intended to work *out of the box*
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- [x] easy to use even for FPGA/RISC-V starters – intended to work *out of the box*
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## NEORV32 Processor Features
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## 2. NEORV32 Processor Features
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The NEORV32 Processor (top entity: [`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd))
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The NEORV32 Processor (top entity: [`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd))
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provides a full-featured SoC build around the NEORV32 CPU. It is highly configurable via generics
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provides a full-featured SoC build around the NEORV32 CPU. It is highly configurable via generics
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to allow a flexible customization according to your needs. Note that all modules listed below are _optional_.
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to allow a flexible customization according to your needs. Note that all modules listed below are _optional_.
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In-depth detailed information regarding the processor/SoC can be found in the :books:
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In-depth detailed information regarding the processor/SoC can be found in the :books:
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**SoC Connectivity and Integration**
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**SoC Connectivity and Integration**
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* 32-bit external bus interface, Wishbone b4 compatible
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* 32-bit external bus interface, Wishbone b4 compatible
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([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
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([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
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* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd) for AXI4-Lite master interface
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* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd) for AXI4-Lite master interface
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* 32-bit stram link interface with up to 8 independent RX and TX links
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* 32-bit stream link interface with up to 8 independent RX and TX links
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([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))
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([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))
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* AXI4-Stream compatible
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* AXI4-Stream compatible
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* external interrupt controller with up to 32 channels
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* external interrupt controller with up to 32 channels
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([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
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([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
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* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
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* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### FPGA Implementation Results - Processor
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### FPGA Implementation Results - Processor
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The hardware resources used by a specifc processor setup is defined by the implemented CPU extensions
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The hardware resources used by a specific processor setup is defined by the implemented CPU extensions
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([see below](#FPGA-Implementation-Results---CPU)), the configuration of the peripheral modules and some "glue logic".
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([see below](#FPGA-Implementation-Results---CPU)), the configuration of the peripheral modules and some "glue logic".
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Section [_"FPGA Implementation Results - Processor Modules"_](https://stnolting.github.io/neorv32/#_processor_modules)
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Section [_"FPGA Implementation Results - Processor Modules"_](https://stnolting.github.io/neorv32/#_processor_modules)
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of the online datasheet shows the ressource utilization of each optional processor module to allow an
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of the online datasheet shows the resource utilization of each optional processor module to allow an
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estimation of the actual setup's hardware requirements.
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estimation of the actual setup's hardware requirements.
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:information_source: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary FPGA
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:information_source: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary FPGA
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setups targeting various FPGA boards and toolchains. These setups also provide ressource utilization reports for different
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setups targeting various FPGA boards and toolchains. These setups also provide resource utilization reports for different
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SoC configurations
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SoC configurations
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## NEORV32 CPU Features
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## 3. NEORV32 CPU Features
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:books: In-depth detailed information regarding the CPU can be found in the
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:books: In-depth detailed information regarding the CPU can be found in the
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[online documentation - _"NEORV32 Central Processing Unit"_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu).
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[online documentation - _"NEORV32 Central Processing Unit"_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu).
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The CPU (top entity: [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd))
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The CPU (top entity: [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd))
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implements the RISC-V 32-bit `rv32` ISA with optional extensions (see below). It is compatible to a subset of the
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implements the RISC-V 32-bit `rv32` ISA with optional extensions (see below). It is compatible to subsets of the
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*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
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*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
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and a subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
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and the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
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Compatiility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test)
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Compatibility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test)
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(see [`sim/README`](sim/README.md)).
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(see [`sim/README`](sim/README.md)).
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The core implements a little-endian von-Neumann architecture using two pipeline stages. Each stage uses a multi-cycle processing
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The core implements a little-endian Von-Neumann architecture using two pipeline stages, where each stage can operate in a multi-cycle processing
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scheme. The CPU supports three privilege levels (`machine` and optional `user` and `debug_mode`), three standard RISC-V machine
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scheme. The CPU supports three privilege levels (`machine` and optional `user` and `debug_mode`), the three standard RISC-V machine
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interrupts (`MTI`, `MEI`, `MSI`), a single non-maskable interrupt plus 16 _fast interrupt requests_ as custom extensions.
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interrupts (`MTI`, `MEI`, `MSI`) plus 16 _fast interrupt requests_ as custom extensions.
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It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
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It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
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instruction, breakpoint, environment call)
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instruction, breakpoint, environment calls). See :books: [_"Full Virtualization"_](https://stnolting.github.io/neorv32/#_full_virtualization)
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(see :books: [_"Full Virtualization"_](https://stnolting.github.io/neorv32/#_full_virtualization)).
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for more information.
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### Available ISA Extensions
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### Available ISA Extensions
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Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
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Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
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[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
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[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
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[[`HPM`](https://stnolting.github.io/neorv32/#_hpm_hardware_performance_monitors)]
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[[`HPM`](https://stnolting.github.io/neorv32/#_hpm_hardware_performance_monitors)]
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[[`DEBUG`](https://stnolting.github.io/neorv32/#_cpu_debug_mode)]**
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[[`DEBUG`](https://stnolting.github.io/neorv32/#_cpu_debug_mode)]**
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:warning: The `Zbb`, `Zfinx` and `Zmmul` RISC-V extensions are frozen but not officially ratified yet. Hence, there is no
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:warning: The `Zbb`, `Zfinx` and `Zmmul` RISC-V extensions are frozen but not officially ratified yet. Hence, there is no
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upstream gcc support. To circumvence this, the NEORV32 software framework provides _intrinsic_ libraries for these extensions.
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upstream gcc support. To circumvent this, the NEORV32 software framework provides _intrinsic_ libraries for these extensions.
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### FPGA Implementation Results - CPU
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### FPGA Implementation Results - CPU
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|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
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|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
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| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
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| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
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| `rv32i_Zicsr` | 1729 | 813 | 1024 | 0 | 124 MHz |
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| `rv32i_Zicsr` | 1729 | 813 | 1024 | 0 | 124 MHz |
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| `rv32imac_Zicsr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
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| `rv32imac_Zicsr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
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:information_source: An incremental list of CPU exntension's hardware utilization can found in
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:information_source: An incremental list of CPU extension's hardware utilization can found in
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[online documentation - _"FPGA Implementation Results - CPU"_](https://stnolting.github.io/neorv32/#_cpu).
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[online documentation - _"FPGA Implementation Results - CPU"_](https://stnolting.github.io/neorv32/#_cpu).
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:information_source: The CPU provides options to further reduce the footprint (for example by constraining
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:information_source: The CPU provides options to further reduce the footprint (for example by constraining
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the CPU-internal counters). See the [online data](https://stnolting.github.io/neorv32) sheet for more information.
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the CPU-internal counters). See the [online data](https://stnolting.github.io/neorv32) sheet for more information.
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### Performance
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### Performance
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The NEORV32 CPU is based on a two-stages pipelined architecutre. Since both stage use a multi-cycle processing scheme,
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The NEORV32 CPU is based on a two-stages pipelined architecture. Since both stage use a multi-cycle processing scheme,
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each instruction requires several clock cycles to execute (2 cycles for ALU operations, up to 40 cycles for divisions).
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each instruction requires several clock cycles to execute (2 cycles for ALU operations, up to 40 cycles for divisions).
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The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
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The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
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available CPU extensions.
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available CPU extensions.
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The following table shows the performance results (relative CoreMark score and average cycles per instruction) for
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The following table shows the performance results (relative CoreMark score and average cycles per instruction) for
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## Software Framework and Tooling
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## 4. Software Framework and Tooling
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:books: In-depth detailed information regarding the software framework can be found in the
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:books: In-depth detailed information regarding the software framework can be found in the
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[online documentation - _"Software Framework"_](https://stnolting.github.io/neorv32/#_software_framework).
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[online documentation - _"Software Framework"_](https://stnolting.github.io/neorv32/#_software_framework).
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* [core libraries](https://github.com/stnolting/neorv32/tree/master/sw/lib) for high-level usage of the provided functions and peripherals
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* [core libraries](https://github.com/stnolting/neorv32/tree/master/sw/lib) for high-level usage of the provided functions and peripherals
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## Getting Started
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## 5. Getting Started
|
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This overview provides some *quick links* to the most important sections of the
|
This overview provides some *quick links* to the most important sections of the
|
[online Data Sheet](https://stnolting.github.io/neorv32) and the
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[online Data Sheet](https://stnolting.github.io/neorv32) and the
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[online User Guide](https://stnolting.github.io/neorv32/ug).
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[online User Guide](https://stnolting.github.io/neorv32/ug).
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* [General Hardware Setup](https://stnolting.github.io/neorv32/ug/#_general_hardware_setup) - setup a new NEORV32 EDA project
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* [General Hardware Setup](https://stnolting.github.io/neorv32/ug/#_general_hardware_setup) - setup a new NEORV32 EDA project
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* [General Software Setup](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup) - configure the software framework
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* [General Software Setup](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup) - configure the software framework
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* [Application Compilation](https://stnolting.github.io/neorv32/ug/#_application_program_compilation) - compile an application using `make`
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* [Application Compilation](https://stnolting.github.io/neorv32/ug/#_application_program_compilation) - compile an application using `make`
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* [Upload via Bootloader](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart) - upload and execute executables
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* [Upload via Bootloader](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart) - upload and execute executables
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* [Application-Specific Processor Configuration](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration) - tailor the processor to your needs
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* [Application-Specific Processor Configuration](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration) - tailor the processor to your needs
|
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* [Adding Custom Hardware Modules](https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules) - add _your_ custom hardware
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* [Debugging via the On-Chip Debugger](https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger) - step through code *online* and *in-system*
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* [Debugging via the On-Chip Debugger](https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger) - step through code *online* and *in-system*
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* [Simulation](https://stnolting.github.io/neorv32/ug/#_simulating_the_processor) - simulate the whole SoC
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* [Simulation](https://stnolting.github.io/neorv32/ug/#_simulating_the_processor) - simulate the whole SoC
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* [Hello World!](https://stnolting.github.io/neorv32/ug/index.html#_hello_world) - run a quick _"hello world"_ simulation
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* [Hello World!](https://stnolting.github.io/neorv32/ug/index.html#_hello_world) - run a quick _"hello world"_ simulation
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### :copyright: Legal
|
### :copyright: Legal
|
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Continous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).
|
Continous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).
|
|
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--------
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--------
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Made with :coffee: in Hannover, Germany :eu:
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Made with :coffee: in Hanover, Germany :eu:
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Made with :coffee: in Hanover, Germany :eu:
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Made with :coffee: in Hanover, Germany :eu:
|
