| Line 11... |
Line 11... |
# The NEORV32 RISC-V Processor
|
# The NEORV32 RISC-V Processor
|
|
|
[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
|
[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
|
[](https://github.com/stnolting/neorv32/releases)
|
[](https://github.com/stnolting/neorv32/releases)
|
[](https://doi.org/10.5281/zenodo.5018888)
|
[](https://doi.org/10.5281/zenodo.5018888)
|
|
\
|
[](https://github.com/stnolting/neorv32/releases/tag/nightly)
|
[](https://github.com/stnolting/neorv32/releases/tag/nightly)
|
[](https://stnolting.github.io/neorv32)
|
[](https://stnolting.github.io/neorv32)
|
[](https://github.com/stnolting/neorv32/releases/tag/nightly)
|
[](https://github.com/stnolting/neorv32/releases/tag/nightly)
|
[](https://stnolting.github.io/neorv32/ug)
|
[](https://stnolting.github.io/neorv32/ug)
|
[](https://stnolting.github.io/neorv32/sw/files.html)
|
[](https://stnolting.github.io/neorv32/sw/files.html)
|
| Line 44... |
Line 44... |
|
|
Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
|
Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
|
Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions
|
Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions
|
are executed. Whenever an unexpected situation occurs, the application code is informed via hardware exceptions.
|
are executed. Whenever an unexpected situation occurs, the application code is informed via hardware exceptions.
|
|
|
:information_source: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
|
:thinking: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
|
|
|
:books: For detailed information take a look at the [NEORV32 documentation (online at GitHub-pages)](https://stnolting.github.io/neorv32/).
|
:books: For detailed information take a look at the [NEORV32 documentation (online at GitHub-pages)](https://stnolting.github.io/neorv32/).
|
The *doxygen*-based documentation of the *software framework* is also available online
|
The *doxygen*-based documentation of the *software framework* is also available online
|
at [GitHub-pages](https://stnolting.github.io/neorv32/sw/files.html).
|
at [GitHub-pages](https://stnolting.github.io/neorv32/sw/files.html).
|
|
|
| Line 57... |
Line 57... |
|
|
:package: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary setups targeting
|
:package: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary setups targeting
|
various FPGA boards and toolchains to get you started. Several example programs (including a FreeRTOS port) to be run on your setup
|
various FPGA boards and toolchains to get you started. Several example programs (including a FreeRTOS port) to be run on your setup
|
can be found in [`sw/example`](https://github.com/stnolting/neorv32/tree/master/sw/example).
|
can be found in [`sw/example`](https://github.com/stnolting/neorv32/tree/master/sw/example).
|
|
|
:kite: Upstream [**Zephyr RTOS**](https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html) support.
|
:kite: Supported by upstream [Zephyr OS](https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html).
|
|
|
:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
|
|
**TODOs**, features being **planned** and **work-in-progress**.
|
|
|
|
:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
|
:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
|
[new discussion](https://github.com/stnolting/neorv32/discussions) if you have questions, comments, ideas or if something is
|
[new discussion](https://github.com/stnolting/neorv32/discussions) if you have questions, comments, ideas or if something is
|
not working as expected. Or have a chat on our [gitter channel](https://gitter.im/neorv32/community).
|
not working as expected. Or have a chat on our [gitter channel](https://gitter.im/neorv32/community).
|
|
|
:rocket: Check out the [quick links below](#Getting-Started) or directly jump to the
|
:rocket: Check out the [quick links below](#5-Getting-Started) or directly jump to the
|
[*User Guide*](https://stnolting.github.io/neorv32/ug/) to get started
|
[*User Guide*](https://stnolting.github.io/neorv32/ug/) to get started
|
setting up your NEORV32 setup!
|
setting up your NEORV32 setup!
|
|
|
|
|
### Project Key Features
|
### Project Key Features
|
|
|
- [x] all-in-one: [CPU](#NEORV32-CPU-Features) plus [Processor/SoC](#NEORV32-Processor-Features) plus [Software Framework & Tooling](#Software-Framework-and-Tooling)
|
- [x] all-in-one: [CPU](#3-NEORV32-CPU-Features) plus [SoC](#2-NEORV32-Processor-Features) plus [Software Framework & Tooling](#4-Software-Framework-and-Tooling)
|
- [x] completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
|
- [x] completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
|
- [x] fully synchronous design, no latches, no gated clocks
|
- [x] fully synchronous design, no latches, no gated clocks
|
- [x] be as small as possible while being as RISC-V-compliant as possible – but with a reasonable size-performance trade-off:
|
- [x] be as small as possible while being as RISC-V-compliant as possible – but with a reasonable size-performance trade-off:
|
the processor (CPU _including_ privileged architecture) fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz
|
the processor (CPU _including_ privileged architecture) fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz
|
- [x] from zero to `printf("hello world!");` - completely open source and documented
|
- [x] from zero to `printf("hello world!");` - completely open source and documented
|
| Line 90... |
Line 87... |
## 2. NEORV32 Processor Features
|
## 2. NEORV32 Processor Features
|
|
|
The NEORV32 Processor (top entity: [`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd))
|
The NEORV32 Processor (top entity: [`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd))
|
provides a full-featured SoC build around the NEORV32 CPU. It is highly configurable via generics
|
provides a full-featured SoC build around the NEORV32 CPU. It is highly configurable via generics
|
to allow a flexible customization according to your needs. Note that all modules listed below are _optional_.
|
to allow a flexible customization according to your needs. Note that all modules listed below are _optional_.
|
In-depth detailed information regarding the processor/SoC can be found in the :books:
|
|
[online documentation - _"NEORV32 Processors (SoC)"_](https://stnolting.github.io/neorv32/#_neorv32_processor_soc).
|
|
|
|
**Memory**
|
**Memory**
|
|
|
* processor-internal data and instruction memories ([DMEM](https://stnolting.github.io/neorv32/#_data_memory_dmem) /
|
* processor-internal data and instruction memories ([DMEM](https://stnolting.github.io/neorv32/#_data_memory_dmem) /
|
[IMEM](https://stnolting.github.io/neorv32/#_instruction_memory_imem)) &
|
[IMEM](https://stnolting.github.io/neorv32/#_instruction_memory_imem)) &
|
cache ([iCACHE](https://stnolting.github.io/neorv32/#_processor_internal_instruction_cache_icache))
|
cache ([iCACHE](https://stnolting.github.io/neorv32/#_processor_internal_instruction_cache_icache))
|
* bootloader ([BOOTLDROM](https://stnolting.github.io/neorv32/#_bootloader_rom_bootrom)) with serial user interface
|
* bootloader ([BOOTLDROM](https://stnolting.github.io/neorv32/#_bootloader_rom_bootrom)) with serial user interface
|
* supports boot via UART or from external SPI flash
|
* allows booting application code via UART or from external SPI flash
|
|
|
**Timers**
|
**Timers**
|
|
|
* machine system timer, 64-bit ([MTIME](https://stnolting.github.io/neorv32/#_machine_system_timer_mtime)), RISC-V spec. compatible
|
* machine system timer, 64-bit ([MTIME](https://stnolting.github.io/neorv32/#_machine_system_timer_mtime)), RISC-V spec. compatible
|
* general purpose 32-bit timer ([GPTMR](https://stnolting.github.io/neorv32/#_general_purpose_timer_gptmr))
|
* general purpose 32-bit timer ([GPTMR](https://stnolting.github.io/neorv32/#_general_purpose_timer_gptmr))
|
| Line 134... |
Line 129... |
for tightly-coupled custom co-processor extensions
|
for tightly-coupled custom co-processor extensions
|
|
|
**Advanced**
|
**Advanced**
|
|
|
* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
|
* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
|
* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) via JTGA - implementing
|
* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) accessible via JTAG interface - implementing
|
the [*Minimal RISC-V Debug Specification Version 0.13.2*](https://github.com/riscv/riscv-debug-spec)
|
the [*Minimal RISC-V Debug Specification Version 0.13.2*](https://github.com/riscv/riscv-debug-spec)
|
and compatible with *OpenOCD* and *gdb*
|
and compatible with *OpenOCD* and *gdb*
|
* bus keeper to monitor processor-internal bus transactions ([BUSKEEPER](https://stnolting.github.io/neorv32/#_internal_bus_monitor_buskeeper))
|
* bus keeper to monitor the CPU's bus transactions ([BUSKEEPER](https://stnolting.github.io/neorv32/#_internal_bus_monitor_buskeeper))
|
|
|
:information_source: It is recommended to use the processor setup even if you want to **use the CPU in stand-alone mode**.
|
|
Just disable all optional processor-internal modules via the according generics and you will get a "CPU wrapper" that
|
|
provides a minimal CPU environment and an external memory interface (like AXI4). This minimal setup allows to further use
|
|
the default bootloader and software framework. From this base you can start building your own processor system.
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### FPGA Implementation Results - Processor
|
### FPGA Implementation Results - Processor
|
|
|
The hardware resources used by a specific processor setup is defined by the implemented CPU extensions
|
The hardware resources used by a specific processor setup is defined by the implemented CPU extensions,
|
([see below](#FPGA-Implementation-Results---CPU)), the configuration of the peripheral modules and some "glue logic".
|
the configuration of the peripheral modules and some "glue logic".
|
Section [_"FPGA Implementation Results - Processor Modules"_](https://stnolting.github.io/neorv32/#_processor_modules)
|
Section [_FPGA Implementation Results - Processor Modules_](https://stnolting.github.io/neorv32/#_processor_modules)
|
of the online datasheet shows the resource utilization of each optional processor module to allow an
|
of the online datasheet shows the resource utilization of each optional processor module to allow an
|
estimation of the actual setup's hardware requirements.
|
estimation of the actual setup's hardware requirements.
|
|
|
:information_source: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary FPGA
|
:information_source: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary FPGA
|
setups targeting various FPGA boards and toolchains. These setups also provide resource utilization reports for different
|
setups targeting various FPGA boards and toolchains. These setups also provide resource utilization reports for different
|
| Line 165... |
Line 155... |
|
|
|
|
|
|
## 3. NEORV32 CPU Features
|
## 3. NEORV32 CPU Features
|
|
|
:books: In-depth detailed information regarding the CPU can be found in the
|
|
[online documentation - _"NEORV32 Central Processing Unit"_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu).
|
|
|
|
The CPU (top entity: [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd))
|
The CPU (top entity: [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd))
|
implements the RISC-V 32-bit `rv32` ISA with optional extensions (see below). It is compatible to subsets of the
|
implements the RISC-V 32-bit `rv32` ISA with optional extensions (see below). It is compatible to subsets of the
|
*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
|
*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
|
and the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
|
and the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
|
Compatibility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test)
|
Compatibility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test)
|
| Line 182... |
Line 169... |
Currently, three privilege levels (`machine` and optional `user` and `debug_mode`) are supported. The CPU implements all three standard RISC-V machine
|
Currently, three privilege levels (`machine` and optional `user` and `debug_mode`) are supported. The CPU implements all three standard RISC-V machine
|
interrupts (`MTI`, `MEI`, `MSI`) plus 16 _fast interrupt requests_ as custom extensions.
|
interrupts (`MTI`, `MEI`, `MSI`) plus 16 _fast interrupt requests_ as custom extensions.
|
It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
|
It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
|
instruction, breakpoint, environment calls).
|
instruction, breakpoint, environment calls).
|
|
|
|
:books: In-depth detailed information regarding the CPU can be found in the
|
|
[_Data Sheet: NEORV32 Central Processing Unit_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu).
|
|
|
|
|
### Available ISA Extensions
|
### Available ISA Extensions
|
|
|
Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
|
Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
|
documentation section). Note that the `X` extension is always enabled.
|
documentation section). Note that the `X` extension is always enabled.
|
| Line 226... |
Line 216... |
|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
|
|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
|
| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
|
| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
|
| `rv32i_Zicsr_Zicntr` | 1729 | 813 | 1024 | 0 | 124 MHz |
|
| `rv32i_Zicsr_Zicntr` | 1729 | 813 | 1024 | 0 | 124 MHz |
|
| `rv32imac_Zicsr_Zicntr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
|
| `rv32imac_Zicsr_Zicntr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
|
|
|
:information_source: An incremental list of CPU extension's hardware utilization can found in
|
:information_source: An incremental list of CPU extension's hardware utilization can found in the
|
[online documentation - _"FPGA Implementation Results - CPU"_](https://stnolting.github.io/neorv32/#_cpu).
|
[_Data Sheet: FPGA Implementation Results - CPU_](https://stnolting.github.io/neorv32/#_cpu).
|
|
|
:information_source: The CPU provides options to further reduce the footprint (for example by constraining
|
:information_source: The CPU (and also the SoC) provides advanced options to optimize for performance, area or energy.
|
the CPU-internal counters). See the [online data](https://stnolting.github.io/neorv32) sheet for more information.
|
See [_User Guide: Application-Specific Processor Configuration_](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration)
|
|
for more information.
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### Performance
|
### Performance
|
| Line 243... |
Line 234... |
each instruction requires several clock cycles to execute (2 cycles for ALU operations, up to 40 cycles for divisions).
|
each instruction requires several clock cycles to execute (2 cycles for ALU operations, up to 40 cycles for divisions).
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
|
available CPU extensions.
|
available CPU extensions.
|
|
|
The following table shows the performance results (relative CoreMark score and average cycles per instruction) for
|
The following table shows the performance results (relative CoreMark score and average cycles per instruction) for
|
_exemplary_ CPU configuration running 2000 iterations of the [CoreMark CPU benchmark](https://www.eembc.org/coremark).
|
_exemplary_ CPU configuration running 2000 iterations of the CoreMark CPU benchmark.
|
The source files are available in [`sw/example/coremark`](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark).
|
The source files are available in [`sw/example/coremark`](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark).
|
|
A simple(!) port of the **Dhrystone** benchmark is also available in
|
:information_source: A _simple_ port of the **Dhrystone** benchmark is also available:
|
[`sw/example/dhrystone`](https://github.com/stnolting/neorv32/blob/master/sw/example/dhrystone).
|
[`sw/example/dhrystone`](https://github.com/stnolting/neorv32/blob/master/sw/example/dhrystone)
|
|
|
|
~~~
|
|
**CoreMark Setup**
|
|
Hardware: 32kB IMEM, 8kB DMEM, no caches, 100MHz clock
|
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
|
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
|
Compiler flags: default, see makefile; optimization -O3
|
|
~~~
|
|
|
|
Results generated for hardware version [`1.5.7.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.5.7.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
| CPU Configuration | CoreMark Score | CoreMarks/MHz | Average CPI |
|
| CPU Configuration | CoreMark Score | CoreMarks/MHz | Average CPI |
|
|:------------------------------------------------|:--------------:|:-------------:|:-----------:|
|
|:------------------------------------------------|:--------------:|:-------------:|:-----------:|
|
| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04** |
|
| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04** |
|
| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34** |
|
| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34** |
|
| _performance_ (`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54** |
|
| _performance_ (`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54** |
|
|
|
:information_source: More information regarding the CPU performance can be found in the
|
:information_source: More information regarding the CPU performance can be found in the
|
[online documentation - _"CPU Performance"_](https://stnolting.github.io/neorv32/#_cpu_performance).
|
[_Data Sheet: CPU Performance_](https://stnolting.github.io/neorv32/#_cpu_performance).
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
## 4. Software Framework and Tooling
|
## 4. Software Framework and Tooling
|
|
|
:books: In-depth detailed information regarding the software framework can be found in the
|
:books: In-depth detailed information regarding the software framework can be found in the
|
[online documentation - _"Software Framework"_](https://stnolting.github.io/neorv32/#_software_framework).
|
[_Data Sheet: Software Framework_](https://stnolting.github.io/neorv32/#_software_framework).
|
|
|
* [core libraries](https://github.com/stnolting/neorv32/tree/master/sw/lib) for high-level usage of the provided functions and peripherals
|
* [core libraries](https://github.com/stnolting/neorv32/tree/master/sw/lib) for high-level usage of the provided functions and peripherals
|
* application compilation based on GNU makefiles
|
* application compilation based on GNU makefiles
|
* gcc-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
|
* gcc-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
|
* bootloader with UART interface console
|
* bootloader with UART interface console
|
* runtime environment for handling traps
|
* runtime environment for handling traps
|
* several [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) to get started including
|
* several [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) to get started including CoreMark, FreeRTOS and Conway's Game of Life
|
[CoreMark](https://github.com/stnolting/neorv32/tree/master/sw/example/coremark),
|
|
[FreeRTOS](https://github.com/stnolting/neorv32/tree/master/sw/example/demo_freeRTOS) and
|
|
[Conway's Game of Life](https://github.com/stnolting/neorv32/tree/master/sw/example/game_of_life)
|
|
* `doxygen`-based documentation, available on :books: [GitHub pages](https://stnolting.github.io/neorv32/sw/files.html)
|
* `doxygen`-based documentation, available on :books: [GitHub pages](https://stnolting.github.io/neorv32/sw/files.html)
|
* supports implementation using open source tooling (GHDL, Yosys and nextpnr; in the future Verilog-to-Routing); both, software and hardware can be
|
* supports implementation using open source tooling (GHDL, Yosys and nextpnr; in the future Verilog-to-Routing); both, software and hardware can be
|
developed and debugged with open source tooling
|
developed and debugged with open source tooling
|
* [continuous integration](https://github.com/stnolting/neorv32/actions) :octocat: is available for:
|
* [continuous integration](https://github.com/stnolting/neorv32/actions) :octocat: is available for:
|
* allowing users to see the expected execution/output of the tools
|
* allowing users to see the expected execution/output of the tools
|
| Line 330... |
Line 309... |
* [Core Libraries](https://stnolting.github.io/neorv32/#_core_libraries) - high-level functions for accessing the processor's peripherals
|
* [Core Libraries](https://stnolting.github.io/neorv32/#_core_libraries) - high-level functions for accessing the processor's peripherals
|
* [Software Framework Documentation](https://stnolting.github.io/neorv32/sw/files.html) - `doxygen`-based documentation
|
* [Software Framework Documentation](https://stnolting.github.io/neorv32/sw/files.html) - `doxygen`-based documentation
|
* [Application Makefiles](https://stnolting.github.io/neorv32/#_application_makefile) - turning your application into an executable
|
* [Application Makefiles](https://stnolting.github.io/neorv32/#_application_makefile) - turning your application into an executable
|
* [Bootloader](https://stnolting.github.io/neorv32/#_bootloader) - the build-in NEORV32 bootloader
|
* [Bootloader](https://stnolting.github.io/neorv32/#_bootloader) - the build-in NEORV32 bootloader
|
|
|
### :rocket: User Guides (see full [User Guide](https://stnolting.github.io/neorv32/ug/))
|
### :rocket: User Guide
|
|
|
* [Toolchain Setup](https://stnolting.github.io/neorv32/ug/#_toolchain_setup) - install and setup RISC-V gcc
|
* [Toolchain Setup](https://stnolting.github.io/neorv32/ug/#_toolchain_setup) - install and setup RISC-V gcc
|
* [General Hardware Setup](https://stnolting.github.io/neorv32/ug/#_general_hardware_setup) - setup a new NEORV32 EDA project
|
* [General Hardware Setup](https://stnolting.github.io/neorv32/ug/#_general_hardware_setup) - setup a new NEORV32 EDA project
|
* [General Software Setup](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup) - configure the software framework
|
* [General Software Setup](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup) - configure the software framework
|
* [Application Compilation](https://stnolting.github.io/neorv32/ug/#_application_program_compilation) - compile an application using `make`
|
* [Application Compilation](https://stnolting.github.io/neorv32/ug/#_application_program_compilation) - compile an application using `make`
|
| Line 355... |
Line 334... |
|
|
|
|
|
|
## Acknowledgements
|
## Acknowledgements
|
|
|
**A big shoutout to all [contributors](https://github.com/stnolting/neorv32/graphs/contributors), who helped improving this project! :heart:**
|
**A big shout-out to the community and all [contributors](https://github.com/stnolting/neorv32/graphs/contributors), who helped improving this project! :heart:**
|
|
|
[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!
|
[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!
|
|
|
Continous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).
|
Continuous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).
|
|
|
--------
|
|
|
|
Made with :coffee: in Hanover, Germany :eu:
|
|
Continuous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).
|
|
