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## 1. Overview
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## 1. Overview
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The NEORV32 Processor is a **customizable microcontroller-like system on chip (SoC)** that is based on the RISC-V NEORV32 CPU.
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The NEORV32 Processor is a **customizable microcontroller-like system on chip (SoC)** that is based on the
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[RISC-V](https://riscv.org/) NEORV32 CPU.
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The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone
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The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone
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custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz.
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custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz.
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Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
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Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
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Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions
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Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions
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:books: For detailed information take a look at the [NEORV32 documentation](https://stnolting.github.io/neorv32/) (online at GitHub-pages).
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:books: For detailed information take a look at the [NEORV32 documentation](https://stnolting.github.io/neorv32/) (online at GitHub-pages).
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:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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To see the changes between _official releases_ visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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To see the changes between _official releases_ visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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:package: [Exemplary setups](https://github.com/stnolting/neorv32/tree/master/setups) targeting
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:package: [**Exemplary setups**](https://github.com/stnolting/neorv32-setups) targeting
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various FPGA boards and toolchains to get you started.
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various FPGA boards and toolchains to get you started.
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:kite: Supported by upstream [Zephyr OS](https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html) and FreeRTOS.
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:kite: Supported by upstream [Zephyr OS](https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html) and FreeRTOS.
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:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
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:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
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### Status
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### Status
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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://stnolting.github.io/neorv32)
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[](https://stnolting.github.io/neorv32)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
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\
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\
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AImplementation)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AWindows)
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## 2. NEORV32 Processor Features
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## 2. NEORV32 Processor Features
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the configuration of the peripheral modules and some "glue logic".
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the configuration of the peripheral modules and some "glue logic".
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Section [_FPGA Implementation Results - Processor Modules_](https://stnolting.github.io/neorv32/#_processor_modules)
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Section [_FPGA Implementation Results - Processor Modules_](https://stnolting.github.io/neorv32/#_processor_modules)
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of the online datasheet shows the resource utilization of each optional processor module to allow an
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of the online datasheet shows the resource utilization of each optional processor module to allow an
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estimation of the actual setup's hardware requirements.
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estimation of the actual setup's hardware requirements.
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The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary FPGA
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:bulb: The [`neorv32-setups`](https://github.com/stnolting/neorv32-setups) repository provides exemplary FPGA
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setups targeting various FPGA boards and toolchains. These setups also provide resource utilization reports for different
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setups targeting various FPGA boards and toolchains. These setups also provide resource utilization reports for different
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SoC configurations. The latest utilization reports for those setups can be found in the report of the
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SoC configurations. The latest utilization reports for those setups can be found in the report of the
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[Implementation Workflow](https://github.com/stnolting/neorv32/actions/workflows/Implementation.yml).
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[Implementation Workflow](https://github.com/stnolting/neorv32-setups/actions/workflows/Implementation.yml).
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### Available ISA Extensions
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### Available ISA Extensions
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Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
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Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
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documentation section). Note that the `X` extension is always enabled.
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documentation section).
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**RV32
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**RV32
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[[`I`](https://stnolting.github.io/neorv32/#_i_base_integer_isa)/
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[[`I`](https://stnolting.github.io/neorv32/#_i_base_integer_isa)/
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[`E`](https://stnolting.github.io/neorv32/#_e_embedded_cpu)]
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[`E`](https://stnolting.github.io/neorv32/#_e_embedded_cpu)]
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[[`A`](https://stnolting.github.io/neorv32/#_a_atomic_memory_access)]
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[[`A`](https://stnolting.github.io/neorv32/#_a_atomic_memory_access)]
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[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
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[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
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[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_integer_multiplication)]
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[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_integer_multiplication)]
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[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
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[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
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[[`DEBUG`](https://stnolting.github.io/neorv32/#_cpu_debug_mode)]**
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[[`DEBUG`](https://stnolting.github.io/neorv32/#_cpu_debug_mode)]**
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:warning: The `B`, `Zfinx` and `Zmmul` RISC-V extensions are frozen but not officially ratified yet. Hence, there is no
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:warning: The `B`, `Zfinx` and `Zmmul` RISC-V are frozen and officially ratified but there is no
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upstream gcc support. To circumvent this, the NEORV32 software framework provides _intrinsic libraries_ for these extensions.
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upstream gcc support yet. To circumvent this, the NEORV32 software framework provides _intrinsic libraries_ for the
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`B` and `Zfinx` extensions.
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### FPGA Implementation Results - CPU
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### FPGA Implementation Results - CPU
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|:------------------------|:----:|:----:|:----:|:-:|:-------:|
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|:------------------------|:----:|:----:|:----:|:-:|:-------:|
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| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
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| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
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| `rv32i_Zicsr_Zicntr` | 1729 | 813 | 1024 | 0 | 124 MHz |
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| `rv32i_Zicsr_Zicntr` | 1729 | 813 | 1024 | 0 | 124 MHz |
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| `rv32imac_Zicsr_Zicntr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
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| `rv32imac_Zicsr_Zicntr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
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:information_source: An incremental list of CPU extension's hardware utilization can found in the
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:bulb: An incremental list of CPU extension's hardware utilization can found in the
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[_Data Sheet: FPGA Implementation Results - CPU_](https://stnolting.github.io/neorv32/#_cpu).
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[_Data Sheet: FPGA Implementation Results - CPU_](https://stnolting.github.io/neorv32/#_cpu).
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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The NEORV32 CPU is based on a two-stages pipeline architecture (fetch and execute).
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The NEORV32 CPU is based on a two-stages pipeline architecture (fetch and execute).
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The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
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The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
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available CPU extensions.
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available CPU extensions.
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The following table shows the performance results (scores and average CPI) for _exemplary_ CPU configurations executing
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The following table shows the performance results (scores and average CPI) for exemplary CPU configurations executing
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2000 iterations of the [CoreMark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) CPU benchmark.
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2000 iterations of the [CoreMark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) CPU benchmark
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(using plain rv32i built-in libraries only!).
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| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)) | CoreMark Score | CoreMarks/MHz | Average CPI |
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| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)) | CoreMark Score | CoreMarks/MHz | Average CPI |
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|:------------------------------------------------|:-----:|:----------:|:--------:|
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|:------------------------------------------------|:-----:|:----------:|:--------:|
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| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04** |
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| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04** |
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| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34** |
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| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34** |
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| _performance_ (`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54** |
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| _performance_ (`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54** |
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:information_source: More information regarding the CPU performance can be found in the
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:bulb: More information regarding the CPU performance can be found in the
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[_Data Sheet: CPU Performance_](https://stnolting.github.io/neorv32/#_cpu_performance).
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[_Data Sheet: CPU Performance_](https://stnolting.github.io/neorv32/#_cpu_performance).
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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* [SVD file](https://github.com/stnolting/neorv32/tree/master/sw/svd) for advanced debugging and IDE integration
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* [SVD file](https://github.com/stnolting/neorv32/tree/master/sw/svd) for advanced debugging and IDE integration
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* bootloader with UART interface console
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* bootloader with UART interface console
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* runtime environment for handling traps
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* runtime environment for handling traps
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* several [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) to get started including CoreMark, FreeRTOS and Conway's Game of Life
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* several [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) to get started including CoreMark, FreeRTOS and Conway's Game of Life
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* doxygen-based documentation, available on [GitHub pages](https://stnolting.github.io/neorv32/sw/files.html)
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* doxygen-based documentation, available on [GitHub pages](https://stnolting.github.io/neorv32/sw/files.html)
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* supports implementation using open source tooling (GHDL, Yosys and nextpnr; in the future: "Verilog-to-Routing") - both, software and hardware can be
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* supports implementation using open source tooling ([GHDL](https://github.com/ghdl/ghdl), Yosys, nextpnr, ...) - both, software and hardware can be
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developed and debugged with open source tooling
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developed and debugged with open source tooling
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* [continuous integration](https://github.com/stnolting/neorv32/actions) is available for:
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* [continuous integration](https://github.com/stnolting/neorv32/actions) is available for:
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* allowing users to see the expected execution/output of the tools
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* allowing users to see the expected execution/output of the tools
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* ensuring specification compliance
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* ensuring specification compliance
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* catching regressions
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* catching regressions
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This is an open-source project that is free of charge. Use this project in any way you like
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This is an open-source project that is free of charge. Use this project in any way you like
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(as long as it complies to the permissive [license](https://github.com/stnolting/neorv32/blob/master/LICENSE)).
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(as long as it complies to the permissive [license](https://github.com/stnolting/neorv32/blob/master/LICENSE)).
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Please quote it appropriately. :+1:
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Please quote it appropriately. :+1:
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We (the community) and I highly appreciate _any_ kind of feedback! Feel free to start a new "show & tell"
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[discussion](https://github.com/stnolting/neorv32/discussions), write some lines on our [gitter channel](https://gitter.im/neorv32/community)
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or directly get in [contact](mailto:stnolting@gmail.com) with me.
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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---------------------------------------
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## Acknowledgements
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**A big shout-out goes to the community and all the [contributors](https://github.com/stnolting/neorv32/graphs/contributors), who helped improving this project! :heart:**
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**A big shout-out goes to the community and all the [contributors](https://github.com/stnolting/neorv32/graphs/contributors), who helped improving this project! :heart:**
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[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!
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Continuous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).
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