| Line 122... |
Line 122... |
([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
|
([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
|
|
|
**Advanced**
|
**Advanced**
|
|
|
* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) accessible via JTAG interface - compliant to
|
* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) accessible via JTAG interface - compliant to
|
the "Minimal RISC-V Debug Specification Version 0.13.2" and compatible with **OpenOCD** + **gdb** and **Segger Embedded Studio**;
|
the "Minimal RISC-V Debug Specification Version 0.13.2" and compatible with **OpenOCD** + **gdb** and **Segger Embedded Studio**
|
includes RISC-V _hardware trigger module_
|
|
* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
|
* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
|
* execute in place module ([XIP](https://stnolting.github.io/neorv32/#_execute_in_place_module_xip)) to directly execute code from SPI flash
|
* execute in place module ([XIP](https://stnolting.github.io/neorv32/#_execute_in_place_module_xip)) to directly execute code from SPI flash
|
* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
|
* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
|
for tightly-coupled custom accelerators and interfaces
|
for tightly-coupled custom accelerators and interfaces
|
* custom functions unit ([CFU](https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu)) for up to 1024
|
* custom functions unit ([CFU](https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu)) for up to 1024
|
| Line 154... |
Line 153... |
|
|
## 3. NEORV32 CPU Features
|
## 3. NEORV32 CPU Features
|
|
|
The NEORV32 CPU implements the RISC-V 32-bit `rv32i` ISA with optional extensions (see below). It is compatible to subsets of the
|
The NEORV32 CPU implements the RISC-V 32-bit `rv32i` ISA with optional extensions (see below). It is compatible to subsets of the
|
*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-spec.pdf)
|
*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-spec.pdf)
|
and the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-privileged.pdf).
|
and the *Privileged Architecture Specification* [(Version 1.12)](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-privileged.pdf).
|
Compatibility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test).
|
Compatibility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test).
|
|
|
The core is a little-endian Von-Neumann machine implemented as multi-cycle architecture.
|
The core is a little-endian Von-Neumann machine implemented as multi-cycle architecture.
|
However, the CPU's_front end (instruction fetch) and back end (instruction execution) can work independently to increase performance.
|
However, the CPU's_front end (instruction fetch) and back end (instruction execution) can work independently to increase performance.
|
Currently, two privilege levels "machine-mode" and optional "user-mode" are supported. The CPU implements all three standard RISC-V machine
|
Currently, two privilege levels "machine-mode" and optional "user-mode" are supported. The CPU implements all three standard RISC-V machine
|
| Line 170... |
Line 169... |
[_Data Sheet: NEORV32 Central Processing Unit_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu).
|
[_Data Sheet: NEORV32 Central Processing Unit_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu).
|
|
|
|
|
### Available ISA Extensions
|
### Available ISA Extensions
|
|
|
Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
|
The following _optional_ RISC-V-compatible and NEORV32-specific ISA extensions are available (linked to the according
|
documentation section).
|
documentation section):
|
|
|
**RV32
|
**RV32
|
[[`I`](https://stnolting.github.io/neorv32/#_i_base_integer_isa)/
|
[[`I`](https://stnolting.github.io/neorv32/#_i_base_integer_isa)/
|
[`E`](https://stnolting.github.io/neorv32/#_e_embedded_cpu)]
|
[`E`](https://stnolting.github.io/neorv32/#_e_embedded_cpu)]
|
[[`A`](https://stnolting.github.io/neorv32/#_a_atomic_memory_access)]
|
[[`A`](https://stnolting.github.io/neorv32/#_a_atomic_memory_access)]
|
| Line 201... |
Line 200... |
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### FPGA Implementation Results - CPU
|
### FPGA Implementation Results - CPU
|
|
|
Implementation results for _exemplary_ CPU configuration generated for an **Intel Cyclone IV EP4CE22F17C6N FPGA**
|
Implementation results for _exemplary_ CPU configuration generated for an **Intel Cyclone IV E** `EP4CE22F17C6` FPGA
|
using **Intel Quartus Prime Lite 20.1** ("balanced implementation, Slow 1200mV 0C Model").
|
using **Intel Quartus Prime Lite 21.1** (no timing constrains, _balanced optimization_, f_max from _Slow 1200mV 0C Model_).
|
|
|
| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md)) | LEs | FFs | Memory bits | DSPs | f_max |
|
| CPU Configuration (version [1.6.8.3](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md)) | LEs | FFs | Memory bits | DSPs | f_max |
|
|:------------------------|:----:|:----:|:----:|:-:|:-------:|
|
|:------------------------|:----:|:----:|:----:|:-:|:-------:|
|
| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
|
| `rv32i_Zicsr` | 1425 | 673 | 1024 | 0 | 118 MHz |
|
| `rv32i_Zicsr_Zicntr` | 1729 | 813 | 1024 | 0 | 124 MHz |
|
| `rv32i_Zicsr_Zicntr` | 1778 | 803 | 1024 | 0 | 118 MHz |
|
| `rv32imac_Zicsr_Zicntr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
|
| `rv32imac_Zicsr_Zicntr` | 2453 | 994 | 1024 | 0 | 118 MHz |
|
|
|
:bulb: An incremental list of CPU extension's hardware utilization can found in the
|
:bulb: An incremental list of the CPUs ISA extension's hardware utilization can found in the
|
[_Data Sheet: FPGA Implementation Results - CPU_](https://stnolting.github.io/neorv32/#_cpu).
|
[_Data Sheet: FPGA Implementation Results - CPU_](https://stnolting.github.io/neorv32/#_cpu).
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
| Line 222... |
Line 221... |
|
|
The NEORV32 CPU is based on a two-stages pipeline architecture (fetch and execute).
|
The NEORV32 CPU is based on a two-stages pipeline architecture (fetch and execute).
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
|
available CPU extensions.
|
available CPU extensions.
|
|
|
The following table shows the performance results (scores and average CPI) for exemplary CPU configurations executing
|
The following table shows the performance results (scores and average CPI) for exemplary CPU configurations (no caches) executing
|
2000 iterations of the [CoreMark](https://github.com/stnolting/neorv32/blob/main/sw/example/coremark) CPU benchmark
|
2000 iterations of the [CoreMark](https://github.com/stnolting/neorv32/blob/main/sw/example/coremark) CPU benchmark
|
(using plain GCC10 rv32i built-in libraries only!).
|
(using plain GCC10 rv32i built-in libraries only!).
|
|
|
| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md)) | CoreMark Score | CoreMarks/MHz | Average CPI |
|
| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md)) | CoreMark Score | CoreMarks/MHz | Average CPI |
|
|:------------------------------------------------|:-----:|:----------:|:--------:|
|
|:------------------------------------------------|:-----:|:----------:|:--------:|
|
| Line 326... |
Line 325... |
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
---------------------------------------
|
---------------------------------------
|
|
|
**A big shout-out goes to the community and all the [contributors](https://github.com/stnolting/neorv32/graphs/contributors), who helped improving this project! :heart:**
|
**:heart: A big shout-out goes to the community and all the [contributors](https://github.com/stnolting/neorv32/graphs/contributors), who helped improving this project!**
|
**:heart: A big shout-out goes to the community and all the [contributors](https://github.com/stnolting/neorv32/graphs/contributors), who helped improving this project!**
|
**:heart: A big shout-out goes to the community and all the [contributors](https://github.com/stnolting/neorv32/graphs/contributors), who helped improving this project!**
|
