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## Introduction
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## Introduction
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The NEORV32 is a customizable mikrocontroller-like processor system based on a RISC-V `rv32i` or `rv32e` CPU with optional
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The NEORV32 is a customizable mikrocontroller-like processor system based on a RISC-V `rv32i` or `rv32e` CPU with optional
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`M`, `C` and `Zicsr` extensions. The CPU was built from scratch and is compliant to the **Unprivileged
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`M`, `C`, `Zicsr` and `Zifencei` extensions. The CPU was built from scratch and is compliant to the **Unprivileged
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ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12**. The NEORV32 is intended
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ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12**. The NEORV32 is intended
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as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller.
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as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller.
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The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI,
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The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI,
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interrupt controller, timers and embedded memories. External memories, peripherals and custom IP can be attached via a
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interrupt controller, timers and embedded memories. External memories, peripherals and custom IP can be attached via a
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### Status
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### Status
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The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/LSE) and can successfully execute
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The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/LSE) and can successfully execute
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
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The processor passes the official `rv32i`, `rv32im`, `rv32imc` and `rv32Zicsr` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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|:--------------------------------------------------------------------------------|:-------|
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|:--------------------------------------------------------------------------------|:-------|
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| [Pre-build toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) |
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| [Pre-build toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_compliance_test) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_compliance_test) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) |
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### Processor Features
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### Processor Features
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- RISC-V-compliant `rv32i` or `rv32e` CPU with optional `C`, `E`, `M` and `Zicsr` extensions
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- RISC-V-compliant `rv32i` or `rv32e` CPU with optional `C`, `E`, `M`, `Zicsr` and `rv32Zifencei` extensions
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- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework
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- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework
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- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
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- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
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- Fully synchronous design, no latches, no gated clocks
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- Fully synchronous design, no latches, no gated clocks
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**RV32I base instruction set** (`I` extension):
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**RV32I base instruction set** (`I` extension):
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* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
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* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
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* System instructions: `ECALL` `EBREAK` `FENCE`
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**Compressed instructions** (`C` extension):
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**Compressed instructions** (`C` extension):
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* ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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* ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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**Integer multiplication and division hardware** (`M` extension):
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**Integer multiplication and division hardware** (`M` extension):
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* Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
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* Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
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* Division instructions: `DIV` `DIVU` `REM` `REMU`
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* Division instructions: `DIV` `DIVU` `REM` `REMU`
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**Privileged architecture** (`Zicsr` extension):
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**Privileged architecture / CSR access** (`Zicsr` extension):
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* Privilege levels: `M-mode` (Machine mode)
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* Privilege levels: `M-mode` (Machine mode)
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* System instructions: `ECALL` `EBREAK` `MRET` `WFI`
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* System instructions: `MRET` `WFI`
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* Counter CSRs: `cycle` `cycleh` `time` `timeh` `instret` `instreth` `mcycle` `mcycleh` `minstret` `minstreth`
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* Counter CSRs: `cycle` `cycleh` `time` `timeh` `instret` `instreth` `mcycle` `mcycleh` `minstret` `minstreth`
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* Machine CSRs: `mstatus` `misa` `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mimpid` `mhartid`
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* Machine CSRs: `mstatus` `misa` `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mimpid` `mhartid`
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* Custom CSRs: `mfeatures` `mclock` `mispacebase` `mdspacebase` `mispacesize` `mdspacesize`
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* Custom CSRs: `mfeatures` `mclock` `mispacebase` `mdspacebase` `mispacesize` `mdspacesize`
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* Supported exceptions and interrupts:
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* Supported exceptions and interrupts:
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* Misaligned instruction address
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* Misaligned instruction address
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* Environment call from M-mode (via `ecall` instruction)
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* Environment call from M-mode (via `ecall` instruction)
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* Machine software instrrupt
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* Machine software instrrupt
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* Machine timer interrupt (via `MTIME` unit)
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* Machine timer interrupt (via `MTIME` unit)
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* Machine external interrupt (via `CLIC` unit)
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* Machine external interrupt (via `CLIC` unit)
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**Privileged architecture / FENCE.I** (`Zifencei` extension):
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* System instructions: `FENCE.I`
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**General**:
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**General**:
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* No hardware support of unaligned accesses - they will trigger and exception
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* No hardware support of unaligned accesses - they will trigger and exception
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* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle execution
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* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle execution
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More information including a detailed list of the available CSRs can be found in
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More information including a detailed list of the available CSRs can be found in
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Memory configuration: Instruction memory --
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-- Memory configuration: Instruction memory --
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
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MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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