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[](https://travis-ci.com/stnolting/neorv32)
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[](https://travis-ci.com/stnolting/neorv32)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/issues)
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[](https://github.com/stnolting/neorv32/pulls)
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[](https://github.com/stnolting/neorv32/commits/master)
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## Table of Content
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## Table of Content
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* [Introduction](#Introduction)
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* [Introduction](#Introduction)
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* [Features](#Features)
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* [Features](#Features)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [Performance](#Performance)
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* [Performance](#Performance)
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* [Top Entity](#Top-Entity)
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* [Top Entity](#Top-Entity)
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* [**Getting Started**](#Getting-Started)
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* [**Getting Started**](#Getting-Started)
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* [Contact](#Contact)
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* [Contribute](#Contribute)
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* [Legal](#Legal)
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* [Legal](#Legal)
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## Introduction
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## Introduction
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ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12**. The NEORV32 is intended
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ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12**. The NEORV32 is intended
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as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller.
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as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller.
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The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI,
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The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI,
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interrupt controller, timers and embedded memories. External memories, peripherals and custom IP can be attached via a
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interrupt controller, timers and embedded memories. External memories, peripherals and custom IP can be attached via a
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Wishbone-based external memory interface. All optional features beyond the base CPU can be enabled configured via VHDL generics.
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Wishbone-based external memory interface. All optional features beyond the base CPU can be enabled and configured via VHDL generics.
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This project comes with a complete software ecosystem that features core libraries for high-level usage of the
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This project comes with a complete software ecosystem that features core libraries for high-level usage of the
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provided functions and peripherals, application makefiles and example programs. All software source files
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provided functions and peripherals, application makefiles and example programs. All software source files
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provide a doxygen-based documentary.
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provide a doxygen-based documentary.
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The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/LSE) and can successfully execute
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The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/LSE) and can successfully execute
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
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The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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| Project | Status |
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|:--------------------------------------------------------------------------------|:-------|
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|:--------------------------------------------------------------------------------|:-------|
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| NEORV32 processor | [](https://travis-ci.com/stnolting/neorv32) |
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| [Pre-build toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) |
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| [Pre-build toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_compliance_test) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_compliance_test) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) |
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#### Limitations to be fixed
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### Limitations to be fixed
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* No exception is triggered in `E`-mode when using registers above `x15` yet
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* No exception is triggered in `E`-mode when using registers above `x15` yet
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#### To-Do / Wish List
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### To-Do / Wish List
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- Synthesis results for more platforms
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- Port Dhrystone benchmark
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- Port Dhrystone benchmark
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- Implement atomic operations (`A` extension)
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- Implement atomic operations (`A` extension)
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- Implement `Zifence` extension
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- Implement co-processor for single-precision floating-point operations (`F` extension)
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- Implement co-processor for single-precision floating-point operations (`F` extension)
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- Implement user mode (`U` extension)
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- Implement user mode (`U` extension)
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- Make a 64-bit branch
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- Make a 64-bit branch
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- Maybe port an RTOS (like [freeRTOS](https://www.freertos.org/) or [RIOT](https://www.riot-os.org/))
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- Maybe port an RTOS (like [freeRTOS](https://www.freertos.org/) or [RIOT](https://www.riot-os.org/))
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* Load address misaligned
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* Load address misaligned
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* Load access fault
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* Load access fault
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* Store address misaligned
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* Store address misaligned
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* Store access fault
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* Store access fault
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* Environment call from M-mode (via `ecall` instruction)
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* Environment call from M-mode (via `ecall` instruction)
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* Machine software instrrupt
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* Machine software instrrupt `msi`
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* Machine timer interrupt (via `MTIME` unit)
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* Machine timer interrupt `mti` (via MTIME unit)
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* Machine external interrupt (via `CLIC` unit)
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* Machine external interrupt `mei` (via CLIC unit)
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**Privileged architecture / FENCE.I** (`Zifencei` extension):
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**Privileged architecture / FENCE.I** (`Zifencei` extension):
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* System instructions: `FENCE.I`
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* System instructions: `FENCE.I`
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**General**:
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**General**:
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| `rv32imc` | `-O2` | 15 208 bytes | 50 | 0.50 |
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| `rv32imc` | `-O2` | 15 208 bytes | 50 | 0.50 |
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### Instruction Cycles
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### Instruction Cycles
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The NEORV32 CPU is based on a multi-cycle architecture. Each instruction is executed in a sequence of several
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The NEORV32 CPU is based on two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
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consecutive micro operations. Hence, each instruction requires several clock cycles to execute. The average CPI
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each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
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(cycles per instruction) depends on the instruction mix of a specific applications and also on the available
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The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available
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CPU extensions.
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CPU extensions.
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Please note that the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
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Please note that the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
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`M` extension use a bit-serial approach and require several cycles for completion.
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`M` extension use a bit-serial approach and require several cycles for completion.
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The following table shows the performance results for successfully running 2000 CoreMark
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The following table shows the performance results for successfully running 2000 CoreMark
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iterations. The average CPI is computed by dividing the total number of required clock cycles (all of CoreMark
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iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by
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dividing the total number of required clock cycles (all of CoreMark
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– not only the timed core) by the number of executed instructions (`instret[h]` CSRs). The executables
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– not only the timed core) by the number of executed instructions (`instret[h]` CSRs). The executables
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were generated using optimization `-O2`.
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were generated using optimization `-O2`.
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| CPU / Toolchain Config. | Required Clock Cycles | Executed Instructions | Average CPI |
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| CPU / Toolchain Config. | Required Clock Cycles | Executed Instructions | Average CPI |
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|:------------------------|----------------------:|----------------------:|:-----------:|
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|:------------------------|----------------------:|----------------------:|:-----------:|
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has been compiled on a 64-bit x86 Ubuntu (Ubuntu on Windows). Download the toolchain of choice:
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has been compiled on a 64-bit x86 Ubuntu (Ubuntu on Windows). Download the toolchain of choice:
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[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
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[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
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### Dowload the Project and Create a Hardware Project
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### Dowload the NEORV32 Project and Create a Hardware Project
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Now its time to get the most recent version the NEORV32 Processor project from GitHub. Clone the NEORV32 repository using
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Now its time to get the most recent version the NEORV32 Processor project from GitHub. Clone the NEORV32 repository using
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`git` from the command line (suggested for easy project updates via `git pull`):
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`git` from the command line (suggested for easy project updates via `git pull`):
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$ git clone https://github.com/stnolting/neorv32.git
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$ git clone https://github.com/stnolting/neorv32.git
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Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain, navigate to an example project like
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Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain, navigate to an example project like
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`sw/example/blink_led` and run:
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`sw/example/blink_led` and run:
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neorv32/sw/example/blink_led$ make check
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neorv32/sw/example/blink_led$ make check
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The NEORV32 project includes some example programs from which you can start your own application:
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The NEORV32 project includes some [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) from
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[SW example projects](https://github.com/stnolting/neorv32/tree/master/sw/example)
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which you can start your own application. Simply compile one of these projects. This will create a NEORV32
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executable `neorv32_exe.bin` in the same folder.
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Simply compile one of these projects. This will create a NEORV32 executable `neorv32_exe.bin` in the same folder.
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neorv32/sw/example/blink_led$ make clean_all compile
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neorv32/sw/example/blink_led$ make clean_all compile
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Connect your FPGA board via UART to you computer and open the according port to interface with the NEORV32 bootloader. The bootloader
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Connect your FPGA board via UART to you computer and open the according port to interface with the NEORV32 bootloader. The bootloader
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uses the following default UART configuration:
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uses the following default UART configuration:
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- 1 stop bit
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- 1 stop bit
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- No parity bits
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- No parity bits
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- No transmission / flow control protocol (raw bytes only)
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- No transmission / flow control protocol (raw bytes only)
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- Newline on `\r\n` (carriage return & newline)
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- Newline on `\r\n` (carriage return & newline)
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Use the bootloader console to upload and execute your application image.
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Use the bootloader console to upload the `neorv32_exe.bin` file and run your application image.
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Going further: Take a look at the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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```
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<< NEORV32 Bootloader >>
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BLDV: Jul 6 2020
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HWV: 1.0.1.0
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CLK: 0x0134FD90 Hz
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MHID: 0x0001CE40
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MISA: 0x42801104
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CONF: 0x03FF0035
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IMEM: 0x00010000 bytes @ 0x00000000
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DMEM: 0x00010000 bytes @ 0x80000000
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Autoboot in 8s. Press key to abort.
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Aborted.
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Available CMDs:
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h: Help
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r: Restart
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u: Upload
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s: Store to flash
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l: Load from flash
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e: Execute
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CMD:> u
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Awaiting neorv32_exe.bin... OK
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CMD:> e
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Booting...
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Blinking LED demo program
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```
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Going further: Take a look at the _Let's Get It Started!_ chapter of the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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## Contact
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If you have any questions, bug reports, ideas or if you are facing problems with the NEORV32 or want to give some kind of feedback, open a
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## Contribute
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[new issue](https://github.com/stnolting/neorv32/issues) or directly drop me a line:
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stnolting@gmail.com
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I'm always thankful for help! So if you have any questions, bug reports, ideas or if you want to give some kind of feedback, feel free
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to open a [new issue](https://github.com/stnolting/neorv32/issues).
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If you want to get involved you can also directly drop me a line (mailto:stnolting@gmail.com).
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Please also check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md).
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## Citation
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## Citation
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## Legal
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## Legal
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This is a hobby project released under the BSD 3-Clause license. No copyright infringement intended.
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This is a hobby project released under the BSD 3-Clause license. No copyright infringement intended.
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Other implied/used projects might have different licensing - see their documentation to get more information.
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Other implied/used projects might have different licensing - see their documentation to get more information.
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**BSD 3-Clause License**
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#### BSD 3-Clause License
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Copyright (c) 2020, Stephan Nolting. All rights reserved.
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Copyright (c) 2020, Stephan Nolting. All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are
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Redistribution and use in source and binary forms, with or without modification, are
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permitted provided that the following conditions are met:
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permitted provided that the following conditions are met:
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Line 550... |
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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OF THE POSSIBILITY OF SUCH DAMAGE.
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OF THE POSSIBILITY OF SUCH DAMAGE.
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#### Limitation of Liability for External Links
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Our website contains links to the websites of third parties („external links“). As the
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content of these websites is not under our control, we cannot assume any liability for
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such external content. In all cases, the provider of information of the linked websites
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is liable for the content and accuracy of the information provided. At the point in time
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when the links were placed, no infringements of the law were recognisable to us. As soon
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as an infringement of the law becomes known to us, we will immediately remove the
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link in question.
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#### Propretary Notice
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"Windows" is a trademark of Microsoft Corporation.
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"Windows" is a trademark of Microsoft Corporation.
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"Artix" and "Vivado" are trademarks of Xilinx Inc.
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"Artix" and "Vivado" are trademarks of Xilinx Inc.
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"Cyclone", "Quartus Prime" and "Avalon Bus" are trademarks of Intel Corporation.
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"Cyclone", "Quartus Prime" and "Avalon Bus" are trademarks of Intel Corporation.
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"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
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"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
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"AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
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"AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
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#### Misc
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|
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[](https://travis-ci.com/stnolting/neorv32)
|
[](https://travis-ci.com/stnolting/neorv32)
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Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).
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Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).
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