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image::riscv_logo.png[width=350,align=center]
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image::riscv_logo.png[width=350,align=center]
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**Key Features**
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**Key Features**
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* 32-bit pipelined/multi-cycle in-order `rv32` RISC-V CPU
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* 32-bit pipelined/multi-cycle in-order `rv32` RISC-V CPU
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* Optional RISC-V extensions: `rv32[i/e][m][a][c][u]` + `[Zfinx][Zicsr][Zifencei]` + `[debug_mode]` (for on-chip debugging)
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* Optional RISC-V extensions:
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** `A` - atomic memory access operations
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** `C` - 16-bit compressed instructions
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** `I` - integer base ISA (always enabled)
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** `E` - embedded CPU version (reduced register file size)
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** `M` - integer multiplication and division hardware
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** `U` - less-privileged _user_ mode
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** `Zfinx` - single-precision floating-point unit
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** `Zicsr` - control and status register access (privileged architecture)
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** `Zifencei` - instruction stream synchronization
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** `Zmmul` - integer multiplication hardware
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** `PMP` - physical memory protection
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** `HPM` - hardware performance monitors
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** `DB` - debug mode
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* Compatible to the RISC-V user specifications and a subset of the RISC-V privileged architecture specifications – passes the official RISC-V Architecture Tests (v2+)
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* Compatible to the RISC-V user specifications and a subset of the RISC-V privileged architecture specifications – passes the official RISC-V Architecture Tests (v2+)
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* Official RISC-V open-source architecture ID
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* Official RISC-V open-source architecture ID
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* Standard RISC-V interrupts (_external_, _timer_, _software_) plus 16 _fast_ interrupts and 1 non-maskable interrupt
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* Standard RISC-V interrupts (_external_, _timer_, _software_) plus 16 _fast_ interrupts and 1 non-maskable interrupt
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* Supports most of the traps from the RISC-V specifications (including bus access exceptions) and traps on all unimplemented/illegal/malformed instructions
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* Supports most of the traps from the RISC-V specifications (including bus access exceptions) and traps on all unimplemented/illegal/malformed instructions
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* Optional physical memory configuration (PMP), compatible to the RISC-V specifications
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* Optional physical memory configuration (PMP), compatible to the RISC-V specifications
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[frame="all",grid="none"]
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[frame="all",grid="none"]
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|======
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|======
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| **CPU_BOOT_ADDR** | _std_ulogic_vector(31 downto 0)_ | 0x00000000
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| **CPU_BOOT_ADDR** | _std_ulogic_vector(31 downto 0)_ | 0x00000000
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3+| This address defines the reset address at which the CPU starts fetching instructions after reset. In terms of the NEORV32 processor, this
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3+| This address defines the reset address at which the CPU starts fetching instructions after reset. In terms of the NEORV32 processor, this
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generic is configured with the base address of the bootloader ROM (default) or with the base address of the processor-internal instruction
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generic is configured with the base address of the bootloader ROM (default) or with the base address of the processor-internal instruction
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memory (IMEM) if the bootloader is disabled (_BOOTLOADER_EN_ = _false_). See section <<_address_space>> for more information.
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memory (IMEM) if the bootloader is disabled (_INT_BOOTLOADER_EN_ = _false_). See section <<_address_space>> for more information.
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|======
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|======
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[cols="4,4,2"]
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[cols="4,4,2"]
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[frame="all",grid="none"]
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[frame="all",grid="none"]
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|======
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|======
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* memory: `lb`, `lh`, `lw`, `lbu`, `lhu`, `sb`, `sh`, `sw`
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* memory: `lb`, `lh`, `lw`, `lbu`, `lhu`, `sb`, `sh`, `sw`
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* alu: `addi`, `slti`, `sltiu`, `xori`, `ori`, `andi`, `slli`, `srli`, `srai`, `add`, `sub`, `sll`, `slt`, `sltu`, `xor`, `srl`, `sra`, `or`, `and`
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* alu: `addi`, `slti`, `sltiu`, `xori`, `ori`, `andi`, `slli`, `srli`, `srai`, `add`, `sub`, `sll`, `slt`, `sltu`, `xor`, `srl`, `sra`, `or`, `and`
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* environment: `ecall`, `ebreak`, `fence`
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* environment: `ecall`, `ebreak`, `fence`
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[NOTE]
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[NOTE]
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In order to keep the hardware footprint low, the CPU's shift unit uses a hybrid parallel/serial approach. Shift
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In order to keep the hardware footprint low, the CPU's shift unit uses a bit-serial serial approach. Hence, shift operations
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operations are split in coarse shifts (multiples of 4) and a final fine shift (0 to 3). The total execution
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take up to 32 cycles (plus overhead) depending on the actual shift amount. Alternatively, the shift operations can be processed
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time depends on the shift amount. Alternatively, the shift operations can be processed completely in parallels by a fast
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completely in parallels by a fast (but large) barrel shifter when the `FAST_SHIFT_EN` generic is _true_. In that case, shift operations
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(but large) barrel shifter when the `FAST_SHIFT_EN` generic is _true_. In that case, shift operations
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complete within 2 cycles (plus overhead) regardless of the actual shift amount.
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complete within 2 cycles regardless of the shift amount. Shift operations can also be executed in a pure serial manner when
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then `TINY_SHIFT_EN` generic is _true_. In that case, shift operations take up to 32 cycles depending on the shift amount.
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[NOTE]
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[NOTE]
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Internally, the `fence` instruction does not perform any operation inside the CPU. It only sets the
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Internally, the `fence` instruction does not perform any operation inside the CPU. It only sets the
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top’s `d_bus_fence_o` signal high for one cycle to inform the memory system a `fence` instruction has been
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top’s `d_bus_fence_o` signal high for one cycle to inform the memory system a `fence` instruction has been
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executed. Any flags within the `fence` instruction word are ignore by the hardware.
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executed. Any flags within the `fence` instruction word are ignore by the hardware.
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Hardware-accelerated integer multiplication and division instructions are available when the
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Hardware-accelerated integer multiplication and division instructions are available when the
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`CPU_EXTENSION_RISCV_M` configuration generic is _true_. In this case the following instructions are
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`CPU_EXTENSION_RISCV_M` configuration generic is _true_. In this case the following instructions are
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available:
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available:
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• multiplication: `mul`, `mulh`, `mulhsu`, `mulhu`
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* multiplication: `mul`, `mulh`, `mulhsu`, `mulhu`
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• division: `div`, `divu`, `rem`, `remu`
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* division: `div`, `divu`, `rem`, `remu`
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[NOTE]
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[NOTE]
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By default, multiplication and division operations are executed in a bit-serial approach.
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By default, multiplication and division operations are executed in a bit-serial approach.
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Alternatively, the multiplier core can be implemented using DSP blocks if the `FAST_MUL_EN`
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Alternatively, the multiplier core can be implemented using DSP blocks if the `FAST_MUL_EN`
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generic is _true_ allowing faster execution. Multiplications and divisions
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generic is _true_ allowing faster execution. Multiplications and divisions
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always require a fixed amount of cycles to complete - regardless of the input operands.
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always require a fixed amount of cycles to complete - regardless of the input operands.
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==== **`Zmmul`** - Integer Multiplication
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This is a _sub-extension_ of the `M` ISA extension. It implements the multiplication-only operations
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of the `M` extensions and is intended for small scale applications, that require hardware-based
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integer multiplications but not hardware-based divisions, which will be computed entirely in software.
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This extension requires only ~50% of the hardware utilization of the `M` extension.
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* multiplication: `mul`, `mulh`, `mulhsu`, `mulhu`
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If `Zmmul` is enabled, executing any division instruction from the `M` ISA (`div`, `divu`, `rem`, `remu`)
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will raise an illegal instruction exception.
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Note that `M` and `Zmmul` extensions _cannot_ be enabled in parallel.
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[TIP]
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If your RISC-V GCC toolchain does not (yet) support the `_Zmmul` ISA extensions, it can be "emulated"
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using a `rv32im` machine architecture and setting the `-mno-div` compiler flag
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(example `$ make MARCH=-march=rv32im USER_FLAGS+=-mno-div clean_all exe`).
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==== **`U`** - Less-Privileged User Mode
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==== **`U`** - Less-Privileged User Mode
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Adds the less-privileged _user mode_ when the `CPU_EXTENSION_RISCV_U` configuration generic is _true_. For
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Adds the less-privileged _user mode_ when the `CPU_EXTENSION_RISCV_U` configuration generic is _true_. For
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instance, use-level code cannot access machine-mode CSRs. Furthermore, access to the address space (like
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instance, use-level code cannot access machine-mode CSRs. Furthermore, access to the address space (like
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peripheral/IO devices) can be limited via the physical memory protection (_PMP_) unit for code running in user mode.
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peripheral/IO devices) can be limited via the physical memory protection (_PMP_) unit for code running in user mode.
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|=======================
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|=======================
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| Class | ISA | Instruction(s) | Execution cycles
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| Class | ISA | Instruction(s) | Execution cycles
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| ALU | `I/E` | `addi` `slti` `sltiu` `xori` `ori` `andi` `add` `sub` `slt` `sltu` `xor` `or` `and` `lui` `auipc` | 2
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| ALU | `I/E` | `addi` `slti` `sltiu` `xori` `ori` `andi` `add` `sub` `slt` `sltu` `xor` `or` `and` `lui` `auipc` | 2
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| ALU | `C` | `c.addi4spn` `c.nop` `c.addi` `c.li` `c.addi16sp` `c.lui` `c.andi` `c.sub` `c.xor` `c.or` `c.and` `c.add` `c.mv` | 2
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| ALU | `C` | `c.addi4spn` `c.nop` `c.addi` `c.li` `c.addi16sp` `c.lui` `c.andi` `c.sub` `c.xor` `c.or` `c.and` `c.add` `c.mv` | 2
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| ALU | `I/E` | `slli` `srli` `srai` `sll` `srl` `sra` | 3 + SAfootnote:[Shift amount.]/4 + SA%4; FAST_SHIFTfootnote:[Barrel shift when `FAST_SHIFT_EN` is enabled.]: 4; TINY_SHIFTfootnote:[Serial shift when `TINY_SHIFT_EN` is enabled.]: 2..32
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| ALU | `I/E` | `slli` `srli` `srai` `sll` `srl` `sra` | 3 + SAfootnote:[Shift amount.]/4 + SA%4; FAST_SHIFTfootnote:[Barrel shift when `FAST_SHIFT_EN` is enabled.]: 4; TINY_SHIFTfootnote:[Serial shift when `TINY_SHIFT_EN` is enabled.]: 2..32
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| ALU | `C` | `c.srli` `c.srai` `c.slli` | 3 + SAfootnote:[Shift amount.]/4 + SA%4; FAST_SHIFTfootnote:[Barrel shift when `FAST_SHIFT_EN` is enabled.]: 4; TINY_SHIFTfootnote:[Serial shift when `TINS_SHIFT_EN` is enabled.]: 2..32
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| ALU | `C` | `c.srli` `c.srai` `c.slli` | 3 + SAfootnote:[Shift amount (0..31).]; FAST_SHIFTfootnote:[Barrel shifter when `FAST_SHIFT_EN` is enabled.]:
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| Branches | `I/E` | `beq` `bne` `blt` `bge` `bltu` `bgeu` | Taken: 5 + MLfootnote:[Memory latency.]; Not taken: 3
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| Branches | `I/E` | `beq` `bne` `blt` `bge` `bltu` `bgeu` | Taken: 5 + MLfootnote:[Memory latency.]; Not taken: 3
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| Branches | `C` | `c.beqz` `c.bnez` | Taken: 5 + MLfootnote:[Memory latency.]; Not taken: 3
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| Branches | `C` | `c.beqz` `c.bnez` | Taken: 5 + MLfootnote:[Memory latency.]; Not taken: 3
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| Jumps / Calls | `I/E` | `jal` `jalr` | 4 + ML
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| Jumps / Calls | `I/E` | `jal` `jalr` | 4 + ML
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| Jumps / Calls | `C` | `c.jal` `c.j` `c.jr` `c.jalr` | 4 + ML
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| Jumps / Calls | `C` | `c.jal` `c.j` `c.jr` `c.jalr` | 4 + ML
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| Memory access | `I/E` | `lb` `lh` `lw` `lbu` `lhu` `sb` `sh` `sw` | 4 + ML
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| Memory access | `I/E` | `lb` `lh` `lw` `lbu` `lhu` `sb` `sh` `sw` | 4 + ML
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// ####################################################################################################################
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// ####################################################################################################################
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:sectnums:
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:sectnums:
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==== Traps, Exceptions and Interrupts
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==== Traps, Exceptions and Interrupts
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In this document a (maybe) special nomenclature regarding traps is used:
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In this document the following nomenclature regarding traps is used:
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* _interrupt_ = asynchronous exceptions
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* _interrupt_ = asynchronous exceptions
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* _exceptions_ = synchronous exceptions
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* _exceptions_ = synchronous exceptions
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* _traps_ = exceptions + interrupts (synchronous or asynchronous exceptions)
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* _traps_ = exceptions + interrupts (synchronous or asynchronous exceptions)
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Whenever an exception or interrupt is triggered, the CPU transfers control to the address stored in the `mtvec`
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Whenever an exception or interrupt is triggered, the CPU transfers control to the address stored in `mtvec`
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CSR. The cause of the according interrupt or exception can be determined via the content of the `mcause`
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CSR. The cause of the according interrupt or exception can be determined via the content of `mcause`
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CSR The address that reflected the current program counter when a trap was taken is stored to `mepc`.
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CSR. The address that reflects the current program counter when a trap was taken is stored to `mepc` CSR.
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Additional information regarding the cause of the trap can be retrieved from `mtval`.
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Additional information regarding the cause of the trap can be retrieved from `mtval` CSR.
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The traps are prioritized. If several exceptions occur at once only the one with highest priority is triggered. If
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The traps are prioritized. If several _exceptions_ occur at once only the one with highest priority is triggered
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several interrupts trigger at once, the one with highest priority is triggered while the remaining ones are
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while all remaining exceptions are ignored. If several _interrupts_ trigger at once, the one with highest priority
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queued. After completing the interrupt handler the interrupt with the second highest priority will issues and
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is serviced first while the remaining ones are queued. After completing the interrupt handler the interrupt with
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so on.
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the second highest priority will get serviced and so on until no further interrupt are pending.
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**Memory Access Exceptions**
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If a load operation causes any exception, the destination register is not written at all. Exceptions caused by a
|
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misalignment or a physical memory protection fault do not trigger a bus read-operation at all.
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Exceptions caused by a store address misalignment or a store physical memory protection fault do not trigger
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a bus write-operation at all.
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**Instruction Atomicity**
|
.Trigger Type
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[IMPORTANT]
|
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All CPU interrupt request signals are high-level triggered. So an interrupt request will be generated if the
|
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according signal is _high_ for exactly one cycle (being high for several cycles might cause multiple
|
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triggering of the same interrupt).
|
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|
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.Instruction Atomicity
|
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[NOTE]
|
All instructions execute as atomic operations – interrupts can only trigger between two instructions.
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All instructions execute as atomic operations – interrupts can only trigger between two instructions.
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**Custom Fast Interrupt Request Lines**
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:sectnums:
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==== Memory Access Exceptions**
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If a load operation causes any exception, the instruction's destination register is
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_not written_ at all. Load exceptions caused by a misalignment or a physical memory protection fault do not
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trigger a bus read-operation at all. Exceptions caused by a store address misalignment or a store physical
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memory protection fault do not trigger
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a bus write-operation at all.
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:sectnums:
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==== Custom Fast Interrupt Request Lines
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As a custom extension, the NEORV32 CPU features 16 fast interrupt request lines via the `firq_i` CPU (/Processor) top
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As a custom extension, the NEORV32 CPU features 16 fast interrupt request (FIRQ) lines via the `firq_i` CPU top
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entity signals. These interrupts have custom configuration and status flags in the `mie` and `mip` CSRs and also
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entity signals. These interrupts have custom configuration and status flags in the `mie` and `mip` CSRs and also
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provide custom trap codes in `mcause`.
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provide custom trap codes in `mcause`. Thes FIRQs are reserved for processor-internal usage only.
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**Non-Maskable Interrupt**
|
:sectnums:
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==== Non-Maskable Interrupt
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The NEORV32 CPU features a single non-maskable interrupt source via the `nm_irq_i` CPU (/Processor) top
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The NEORV32 CPU features a single non-maskable interrupt source via the `nm_irq_i` CPU (/Processor) top
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entity signal that can be used to signal critical system conditions. This interrupt source _cannot_ be disabled at all (even not in interrupt service routines).
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entity signal. This interrupt can be used to signal _critical_ system conditions that need immediate handling.
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The non-maskable interrupt _cannot_ be masked/disabled at all (even not in interrupt service routines).
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Hence, it does _not_ provide configuration/status flags in the `mie` and `mip` CSRs. The RISC-V-compatible
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Hence, it does _not_ provide configuration/status flags in the `mie` and `mip` CSRs. The RISC-V-compatible
|
`mcause` value `0x80000000` is used to indicate the non-maskable interrupt.
|
`mcause` value `0x80000000` is used to indicate the non-maskable interrupt.
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[IMPORTANT]
|
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All CPU/Processor interrupt request signals are triggered when the signal is _high_ for exactly one cycle (being high for several cycles might
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cause multiple triggering of the interrupt).
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// ####################################################################################################################
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// ####################################################################################################################
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:sectnums!:
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:sectnums!:
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