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==== **`Zicsr`** Control and Status Register Access / Privileged Architecture
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==== **`Zicsr`** Control and Status Register Access / Privileged Architecture
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The CSR access instructions as well as the exception and interrupt system (= the privileged architecture)
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The CSR access instructions as well as the exception and interrupt system (= the privileged architecture)
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is implemented when the `CPU_EXTENSION_RISCV_Zicsr` configuration generic is _true_.
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is implemented when the `CPU_EXTENSION_RISCV_Zicsr` configuration generic is _true_.
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[IMPORTANT]
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If the `Zicsr` extension is disabled the CPU does not provide any _privileged architecture_ features at all!
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In order to provide the full set of privileged functions that are required to run more complex tasks like
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operating system and to allow a secure execution environment the `Zicsr` extension should always be enabled.
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In this case the following instructions are available:
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In this case the following instructions are available:
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* CSR access: `csrrw`, `csrrs`, `csrrc`, `csrrwi`, `csrrsi`, `csrrci`
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* CSR access: `csrrw`, `csrrs`, `csrrc`, `csrrwi`, `csrrsi`, `csrrci`
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* environment: `mret`, `wfi`
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* environment: `mret`, `wfi`
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[WARNING]
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[NOTE]
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If the `Zicsr` extension is disabled the CPU does not provide any _privileged architecture_ features at all!
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If `rd=x0` for the `csrrw[i]` instructions there will be no actual read access to the according CSR.
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In order to provide the full set of functions and to allow a secure execution
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However, access privileges are still enforced so these instruction variants _do_ cause side-effects
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environment the `Zicsr` extension should always be enabled.
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(the RISC-V spec. state that these combinations "_shall_ not cause any side-effects").
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[NOTE]
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[NOTE]
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The "wait for interrupt instruction" `wfi` works like a sleep command. When executed, the CPU is
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The "wait for interrupt instruction" `wfi` acts like a sleep command. When executed, the CPU is
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halted until a valid interrupt request occurs. To wake up again, the according interrupt source has to
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halted until a valid interrupt request occurs. To wake up again, the according interrupt source has to
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be enabled via the `mie` CSR and the global interrupt enable flag in `mstatus` has to be set.
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be enabled via the `mie` CSR and the global interrupt enable flag in `mstatus` has to be set.
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[NOTE]
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The `wfi` instruction may also be executed in user-mode without causing an exception as <<_mstatus>> bit
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The `wfi` instruction may also be executed in user-mode without causing an exception as <<_mstatus>> bit
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`TW` (timeout wait) is hardwired to zero.
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`TW` (timeout wait) is _hardwired_ to zero.
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==== **`Zicntr`** CPU Base Counters
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==== **`Zicntr`** CPU Base Counters
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