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.Atomic Memory Operations
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.Atomic Memory Operations
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[IMPORTANT]
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[IMPORTANT]
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The `A` CPU extension only implements the `lr.w` and `sc.w` instructions yet.
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The `A` CPU extension only implements the `lr.w` and `sc.w` instructions yet.
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However, these instructions are sufficient to emulate all further atomic memory operations.
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However, these instructions are sufficient to emulate all further atomic memory operations.
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.Bit-Manipulation ISA Extension
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[IMPORTANT]
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The NEORV32 `B` extension only implements the _basic bit-manipulation instructions_ (`Zbb`) subset
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and the _address generation instructions_ (`Zba`) subset yet.
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// ####################################################################################################################
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// ####################################################################################################################
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:sectnums:
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:sectnums:
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=== CPU Top Entity - Signals
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=== CPU Top Entity - Signals
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==== **`B`** - Bit-Manipulation Operations
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==== **`B`** - Bit-Manipulation Operations
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The `B` ISA extension adds instructions for bit-manipulation operations. This extension is enabled if the
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The `B` ISA extension adds instructions for bit-manipulation operations. This extension is enabled if the
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`CPU_EXTENSION_RISCV_B` configuration generic is _true_.
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`CPU_EXTENSION_RISCV_B` configuration generic is _true_.
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The official RISC-V specifications can be found here: https://github.com/riscv/riscv-bitmanip
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The official RISC-V specifications can be found here: https://github.com/riscv/riscv-bitmanip
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A copy of the spec is also available in `docs/references`.
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[IMPORTANT]
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The NEORV32 `B` ISA extension includes the following sub-extensions (according to the RISC-V
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The NEORV32 `B` extension only implements the _basic bit-manipulation instructions_ (`Zbb`) subset
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bit-manipulation spec. v.093) and their corresponding instructions:
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and the _address generation instructions_ (`Zba`) subset yet.
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The `Zbb` sub-extension adds the following instructions:
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* `andn` `orn` `xnor`
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* `clz` `ctz` `cpop`
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* `max` `maxu` `min` `minu`
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* `sext.b` `sext.h` `zext.h`
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* `rol` `ror` `rori`
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* `orc.b` `rev8`
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The `Zba` sub-extension adds the following instructions:
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* `sh1add` `sh2add` `sh3add`
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* **`Zba` - Address-generation instructions**
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** `sh1add` `sh2add` `sh3add`
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* **`Zbb` - Basic bit-manipulation instructions**
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** `andn` `orn` `xnor`
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** `clz` `ctz` `cpop`
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** `max` `maxu` `min` `minu`
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** `sext.b` `sext.h` `zext.h`
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** `rol` `ror` `rori`
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** `orc.b` `rev8`
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* **`Zbc` - Carry-less multiplication instructions**
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** `clmul` `clmulh` `clmulr`
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* **`Zbs` - Single-bit instructions**
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** `bclr` `bclri`
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** `bext` `bexti`
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** `bext` `binvi`
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** `bset` `bseti`
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[TIP]
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[TIP]
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By default, the bit-manipulation unit uses an _iterative_ approach to compute shift-related operations
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By default, the bit-manipulation unit uses an _iterative_ approach to compute shift-related operations
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like `clz` and `rol`. To increase performance (at the cost of additional hardware resources) the
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like `clz` and `rol`. To increase performance (at the cost of additional hardware resources) the
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<<_fast_shift_en>> generic can be enabled to implement full-parallel logic (like barrel shifters) for all
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<<_fast_shift_en>> generic can be enabled to implement full-parallel logic (like barrel shifters) for all
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shift-related `B` instructions.
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shift-related `B` instructions.
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[WARNING]
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[WARNING]
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The `B` extension is frozen but not officially ratified yet. There is no
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The `B` extension is frozen and officially ratified. However, there is no
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software support for this extension in the upstream GCC RISC-V port yet. However, an
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software support for this extension in the upstream GCC RISC-V port yet. An
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intrinsic library is provided to utilize the provided `B` extension features from C-language
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intrinsic library is provided to utilize the provided `B` extension features from C-language
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code (see `sw/example/bitmanip_test`).
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code (see `sw/example/bitmanip_test`) to circumvent this.
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==== **`C`** - Compressed Instructions
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==== **`C`** - Compressed Instructions
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The _compressed_ ISA extension provides 16-bit encodings of commonly used instructions to reduce code space size.
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The _compressed_ ISA extension provides 16-bit encodings of commonly used instructions to reduce code space size.
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| Bit-manipulation - shifts | `B(Zbb)` | `clz` `ctz` | 3 + 0..32
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| Bit-manipulation - shifts | `B(Zbb)` | `clz` `ctz` | 3 + 0..32
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| Bit-manipulation - shifts | `B(Zbb)` | `cpop` | 3 + 32
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| Bit-manipulation - shifts | `B(Zbb)` | `cpop` | 3 + 32
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| Bit-manipulation - shifts | `B(Zbb)` | `rol` `ror` `rori` | 3 + SA
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| Bit-manipulation - shifts | `B(Zbb)` | `rol` `ror` `rori` | 3 + SA
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| Bit-manipulation - single-bit | `B(Zbs)` | `sbset[i]` `sbclr[i]` `sbinv[i]` `sbext[i]` | 3
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| Bit-manipulation - single-bit | `B(Zbs)` | `sbset[i]` `sbclr[i]` `sbinv[i]` `sbext[i]` | 3
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| Bit-manipulation - shifted-add | `B(Zba)` | `sh1add` `sh2add` `sh3add` | 3
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| Bit-manipulation - shifted-add | `B(Zba)` | `sh1add` `sh2add` `sh3add` | 3
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| Bit-manipulation - carry-less multiply | `B(Zbc)` | `clmul` `clmulh` `clmulr` | 3 + 32
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|=======================
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|=======================
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[NOTE]
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[NOTE]
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The presented values of the *floating-point execution cycles* are average values - obtained from
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The presented values of the *floating-point execution cycles* are average values - obtained from
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4096 instruction executions using pseudo-random input values. The execution time for emulating the
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4096 instruction executions using pseudo-random input values. The execution time for emulating the
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