Subversion Repositories neorv32

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== NEORV32 Central Processing Unit (CPU)

== NEORV32 Central Processing Unit (CPU)

image::neorv32_cpu_block.png[width=600,align=center]

image::neorv32_cpu_block.png[width=600,align=center]

**Key Features**

**Key Features**

** `A` - atomic memory access operations

** `A` - atomic memory access operations

** `B` - bit-manipulation instructions

** `B` - bit-manipulation instructions

** `C` - 16-bit compressed instructions

** `C` - 16-bit compressed instructions

** `I` - integer base ISA (always enabled)

** `I` - integer base ISA (always enabled)

** `E` - embedded CPU version (reduced register file size)

** `E` - embedded CPU version (reduced register file size)

** `Zihpm` - hardware performance monitors

** `Zihpm` - hardware performance monitors

** `Zifencei` - instruction stream synchronization

** `Zifencei` - instruction stream synchronization

** `Zmmul` - integer multiplication hardware

** `Zmmul` - integer multiplication hardware

** `Zxcfu` - custom instructions extension

** `Zxcfu` - custom instructions extension

** `PMP` - physical memory protection

** `PMP` - physical memory protection

* Official RISC-V open-source architecture ID

* Official RISC-V open-source architecture ID

** This is a special aspect on _execution safety_ by <<_full_virtualization>>

** This is a special aspect on _execution safety_ by <<_full_virtualization>>

* Optional physical memory configuration (PMP), compatible to the RISC-V specifications

* Optional physical memory configuration (PMP), compatible to the RISC-V specifications

* Optional hardware performance monitors (HPM) for application benchmarking

* Optional hardware performance monitors (HPM) for application benchmarking

[NOTE]

[NOTE]

It is recommended to use the **NEORV32 Processor** as default top instance even if you only want to use the actual

It is recommended to use the **NEORV32 Processor** as default top instance even if you only want to use the actual

CPU. Simply disable all the processor-internal modules via the generics and you will get a "CPU

CPU. Simply disable all the processor-internal modules via the generics and you will get a "CPU

wrapper" that provides a minimal CPU environment and an external bus interface (like AXI4). This

wrapper" that provides a minimal CPU environment and an external bus interface (like AXI4). This

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==== RISC-V Incompatibility Issues and Limitations

==== RISC-V Incompatibility Issues and Limitations

.Read-Only "Read-Write" CSRs

.Read-Only "Read-Write" CSRs

[IMPORTANT]

[IMPORTANT]

The <<_misa>> and <<_mtval>> CSRs in the NEORV32 are _read-only_.

The <<_misa>> and <<_mtval>> CSRs in the NEORV32 are _read-only_.

.Physical Memory Protection

.Physical Memory Protection

[IMPORTANT]

[IMPORTANT]

.Atomic Memory Operations

.Atomic Memory Operations

[IMPORTANT]

[IMPORTANT]

The `A` CPU extension only implements the `lr.w` and `sc.w` instructions yet.

The `A` CPU extension only implements the `lr.w` and `sc.w` instructions yet.

However, these instructions are sufficient to emulate all further atomic memory operations.

However, these instructions are sufficient to emulate all further atomic memory operations.

// ####################################################################################################################

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=== CPU Top Entity - Signals

=== CPU Top Entity - Signals

.NEORV32 CPU top entity signals

.NEORV32 CPU top entity signals

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4+^| **Global Signals**

4+^| **Global Signals**

| `clk_i`          |     1 | in  | global clock line, all registers triggering on rising edge

| `clk_i`          |     1 | in  | global clock line, all registers triggering on rising edge

| `rstn_i`         |     1 | in  | global reset, low-active

| `rstn_i`         |     1 | in  | global reset, low-active

| `sleep_o`        |     1 | out | CPU is in sleep mode when set

| `sleep_o`        |     1 | out | CPU is in sleep mode when set

| `debug_o`        |     1 | out | CPU is in debug mode when set

| `debug_o`        |     1 | out | CPU is in debug mode when set

| `i_bus_rdata_i`  |    32 | in  | read data

| `i_bus_rdata_i`  |    32 | in  | read data

| `i_bus_wdata_o`  |    32 | out | write data (always zero)

| `i_bus_wdata_o`  |    32 | out | write data (always zero)

| `i_bus_ben_o`    |     4 | out | byte enable

| `i_bus_ben_o`    |     4 | out | byte enable

| `i_bus_we_o`     |     1 | out | write transaction (always zero)

| `i_bus_we_o`     |     1 | out | write transaction (always zero)

| `i_bus_re_o`     |     1 | out | read transaction

| `i_bus_re_o`     |     1 | out | read transaction

| `i_bus_lock_o`   |     1 | out | exclusive access request (always zero)

| `i_bus_lock_o`   |     1 | out | exclusive access request (always zero)

| `i_bus_ack_i`    |     1 | in  | bus transfer acknowledge from accessed peripheral

| `i_bus_ack_i`    |     1 | in  | bus transfer acknowledge from accessed peripheral

| `i_bus_err_i`    |     1 | in  | bus transfer terminate from accessed peripheral

| `i_bus_err_i`    |     1 | in  | bus transfer terminate from accessed peripheral

| `d_bus_rdata_i`  |    32 | in  | read data

| `d_bus_rdata_i`  |    32 | in  | read data

| `d_bus_wdata_o`  |    32 | out | write data

| `d_bus_wdata_o`  |    32 | out | write data

| `d_bus_ben_o`    |     4 | out | byte enable

| `d_bus_ben_o`    |     4 | out | byte enable

| `d_bus_we_o`     |     1 | out | write transaction

| `d_bus_we_o`     |     1 | out | write transaction

| `d_bus_re_o`     |     1 | out | read transaction

| `d_bus_re_o`     |     1 | out | read transaction

| `d_bus_lock_o`   |     1 | out | exclusive access request

| `d_bus_lock_o`   |     1 | out | exclusive access request

| `d_bus_ack_i`    |     1 | in  | bus transfer acknowledge from accessed peripheral

| `d_bus_ack_i`    |     1 | in  | bus transfer acknowledge from accessed peripheral

| `d_bus_err_i`    |     1 | in  | bus transfer terminate from accessed peripheral

| `d_bus_err_i`    |     1 | in  | bus transfer terminate from accessed peripheral

4+^| **Interrupts, RISC-V-compatible (<<_traps_exceptions_and_interrupts>>)**

4+^| **Interrupts, RISC-V-compatible (<<_traps_exceptions_and_interrupts>>)**

| `msw_irq_i`      |     1 | in  | RISC-V machine software interrupt

| `msw_irq_i`      |     1 | in  | RISC-V machine software interrupt

| `mext_irq_i`     |     1 | in  | RISC-V machine external interrupt

| `mext_irq_i`     |     1 | in  | RISC-V machine external interrupt

| `mtime_irq_i`    |     1 | in  | RISC-V machine timer interrupt

| `mtime_irq_i`    |     1 | in  | RISC-V machine timer interrupt

| `firq_i`         |    16 | in  | fast interrupt request signals

| `firq_i`         |    16 | in  | fast interrupt request signals

4+^| **Enter Debug Mode Request (<<_on_chip_debugger_ocd>>)**

4+^| **Enter Debug Mode Request (<<_on_chip_debugger_ocd>>)**

| `db_halt_req_i`  |     1 | in  | request CPU to halt and enter debug mode

| `db_halt_req_i`  |     1 | in  | request CPU to halt and enter debug mode

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The _specific_ generics are listed below.

The _specific_ generics are listed below.

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3+| This address defines the reset address at which the CPU starts fetching instructions after reset. In terms of the NEORV32 processor, this

3+| This address defines the reset address at which the CPU starts fetching instructions after reset. In terms of the NEORV32 processor, this

generic is configured with the base address of the bootloader ROM (default) or with the base address of the processor-internal instruction

generic is configured with the base address of the bootloader ROM (default) or with the base address of the processor-internal instruction

memory (IMEM) if the bootloader is disabled (_INT_BOOTLOADER_EN_ = _false_). See section <<_address_space>> for more information.

memory (IMEM) if the bootloader is disabled (_INT_BOOTLOADER_EN_ = _false_). See section <<_address_space>> for more information.

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3+| This address defines the entry address for the "execution based" on-chip debugger. By default, this generic is configured with the base address

3+| This address defines the entry address for the "execution based" on-chip debugger. By default, this generic is configured with the base address

of the debugger memory. See section <<_on_chip_debugger_ocd>> for more information.

of the debugger memory. See section <<_on_chip_debugger_ocd>> for more information.

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3+| Implement RISC-V-compatible "debug" CPU operation mode. See section <<_cpu_debug_mode>> for more information.

3+| Implement RISC-V-compatible "debug" CPU operation mode. See section <<_cpu_debug_mode>> for more information.

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* multiplication: `mul` `mulh` `mulhsu` `mulhu`

* multiplication: `mul` `mulh` `mulhsu` `mulhu`

* division: `div` `divu` `rem` `remu`

* division: `div` `divu` `rem` `remu`

[NOTE]

[NOTE]

By default, multiplication and division operations are executed in a bit-serial approach.

By default, multiplication and division operations are executed in a bit-serial approach.

generic is _true_ allowing faster execution. Multiplications and divisions

generic is _true_ allowing faster execution. Multiplications and divisions

always require a fixed amount of cycles to complete - regardless of the input operands.

always require a fixed amount of cycles to complete - regardless of the input operands.

==== **`Zmmul`** - Integer Multiplication

==== **`Zmmul`** - Integer Multiplication

This is a _sub-extension_ of the `M` ISA extension. It implements the multiplication-only operations

This is a _sub-extension_ of the `M` ISA extension. It implements the multiplication-only operations

of the `M` extensions and is intended for size-constrained setups that require hardware-based

of the `M` extensions and is intended for size-constrained setups that require hardware-based

operation mode. It is implemented if the <<_cpu_extension_riscv_u>> configuration generic is _true_.

operation mode. It is implemented if the <<_cpu_extension_riscv_u>> configuration generic is _true_.

Code executed in user-mode cannot access machine-mode CSRs. Furthermore, user-mode access to the address space (like

Code executed in user-mode cannot access machine-mode CSRs. Furthermore, user-mode access to the address space (like

peripheral/IO devices) can be constrained via the physical memory protection (_PMP_).

peripheral/IO devices) can be constrained via the physical memory protection (_PMP_).

Any kind of privilege rights violation will raise an exception to allow <<_full_virtualization>>.

Any kind of privilege rights violation will raise an exception to allow <<_full_virtualization>>.

==== **`X`** - NEORV32-Specific (Custom) Extensions

==== **`X`** - NEORV32-Specific (Custom) Extensions

The NEORV32-specific extensions are always enabled and are indicated by the set `X` bit in the <<_misa>> CSR.

The NEORV32-specific extensions are always enabled and are indicated by the set `X` bit in the <<_misa>> CSR.

The most important points of the NEORV32-specific extensions are:

The most important points of the NEORV32-specific extensions are:

* All undefined/unimplemented/malformed/illegal instructions do raise an illegal instruction exception (see <<_full_virtualization>>).

* All undefined/unimplemented/malformed/illegal instructions do raise an illegal instruction exception (see <<_full_virtualization>>).

* There are <<_neorv32_specific_csrs>>.

* There are <<_neorv32_specific_csrs>>.

==== **`Zfinx`** Single-Precision Floating-Point Operations

==== **`Zfinx`** Single-Precision Floating-Point Operations

* comparison: `fmin.s` `fmax.s` `feq.s` `flt.s` `fle.s`

* comparison: `fmin.s` `fmax.s` `feq.s` `flt.s` `fle.s`

* computational: `fadd.s` `fsub.s` `fmul.s`

* computational: `fadd.s` `fsub.s` `fmul.s`

* sign-injection: `fsgnj.s` `fsgnjn.s` `fsgnjx.s`

* sign-injection: `fsgnj.s` `fsgnjn.s` `fsgnjx.s`

* number classification: `fclass.s`

* number classification: `fclass.s`

[WARNING]

[WARNING]

Fused multiply-add instructions `f[n]m[add/sub].s` are not supported!

Fused multiply-add instructions `f[n]m[add/sub].s` are not supported!

Division `fdiv.s` and square root `fsqrt.s` instructions are not supported yet!

Division `fdiv.s` and square root `fsqrt.s` instructions are not supported yet!

[NOTE]

[NOTE]

If `rd=x0` for the `csrrw[i]` instructions there will be no actual read access to the according CSR.

If `rd=x0` for the `csrrw[i]` instructions there will be no actual read access to the according CSR.

However, access privileges are still enforced so these instruction variants _do_ cause side-effects

However, access privileges are still enforced so these instruction variants _do_ cause side-effects

(the RISC-V spec. state that these combinations "_shall_ not cause any side-effects").

(the RISC-V spec. state that these combinations "_shall_ not cause any side-effects").

The "wait for interrupt instruction" `wfi` acts like a sleep command. When executed, the CPU is

The "wait for interrupt instruction" `wfi` acts like a sleep command. When executed, the CPU is

be enabled via the <<_mie>> CSR and the global interrupt enable flag in <<_mstatus>> has to be set.

be enabled via the <<_mie>> CSR and the global interrupt enable flag in <<_mstatus>> has to be set.

==== **`Zicntr`** CPU Base Counters

==== **`Zicntr`** CPU Base Counters

The `Zicntr` ISA extension adds the basic cycle `[m]cycle[h]`), instruction-retired (`[m]instret[h]`) and time (`time[h]`)

The `Zicntr` ISA extension adds the basic cycle `[m]cycle[h]`), instruction-retired (`[m]instret[h]`) and time (`time[h]`)

counters. This extensions is stated is _mandatory_ by the RISC-V spec. However, size-constrained setups may remove support for

counters. This extensions is stated is _mandatory_ by the RISC-V spec. However, size-constrained setups may remove support for

these counters. Section <<_machine_counter_and_timer_csrs>> shows a list of all `Zicntr`-related CSRs.

these counters. Section <<_machine_counter_and_timer_csrs>> shows a list of all `Zicntr`-related CSRs.

These are available if the `Zicntr` ISA extensions is enabled via the <<_cpu_extension_riscv_zicntr>> generic.

These are available if the `Zicntr` ISA extensions is enabled via the <<_cpu_extension_riscv_zicntr>> generic.

[NOTE]

[NOTE]

Disabling the `Zicntr` extension does not remove the `time[h]`-driving MTIME unit.

Disabling the `Zicntr` extension does not remove the `time[h]`-driving MTIME unit.

If `Zicntr` is disabled, all accesses to the according counter CSRs will raise an illegal instruction exception.

If `Zicntr` is disabled, all accesses to the according counter CSRs will raise an illegal instruction exception.

==== **`Zihpm`** Hardware Performance Monitors

==== **`Zihpm`** Hardware Performance Monitors

In additions to the base cycle, instructions-retired and time counters the NEORV32 CPU provides

In additions to the base cycle, instructions-retired and time counters the NEORV32 CPU provides

up to 29 hardware performance monitors (HPM 3..31), which can be used to benchmark applications. Each HPM consists of an

up to 29 hardware performance monitors (HPM 3..31), which can be used to benchmark applications. Each HPM consists of an

N-bit wide counter (split in a high-word 32-bit CSR and a low-word 32-bit CSR), where N is defined via the top's

N-bit wide counter (split in a high-word 32-bit CSR and a low-word 32-bit CSR), where N is defined via the top's

<<_hpm_cnt_width>> generic (0..64-bit) and a corresponding event configuration CSR. The event configuration

<<_hpm_cnt_width>> generic (0..64-bit) and a corresponding event configuration CSR. The event configuration

CSR defines the architectural events that lead to an increment of the associated HPM counter.

CSR defines the architectural events that lead to an increment of the associated HPM counter.

The HPM counters are available if the `Zihpm` ISA extensions is enabled via the <<_cpu_extension_riscv_zihpm>> generic.

The HPM counters are available if the `Zihpm` ISA extensions is enabled via the <<_cpu_extension_riscv_zihpm>> generic.

[IMPORTANT]

[IMPORTANT]

are always zero and read-only. Any access from less-privileged modes will raise an illegal instruction

are always zero and read-only. Any access from less-privileged modes will raise an illegal instruction

exception.

exception.

[TIP]

[TIP]

==== **`Zifencei`** Instruction Stream Synchronization

==== **`Zifencei`** Instruction Stream Synchronization

The `Zifencei` CPU extension is implemented if the <<_cpu_extension_riscv_zifencei>> configuration

The `Zifencei` CPU extension is implemented if the <<_cpu_extension_riscv_zifencei>> configuration

the CPU take a look at the memory-mapped <<_custom_functions_subsystem_cfs>>.

the CPU take a look at the memory-mapped <<_custom_functions_subsystem_cfs>>.

==== **`PMP`** Physical Memory Protection

==== **`PMP`** Physical Memory Protection

[TIP]

[TIP]

[source,vhdl]

[source,vhdl]

----

----

-- "critical" number of PMP regions --

-- "critical" number of PMP regions --

constant pmp_num_regions_critical_c : natural := 8;

constant pmp_num_regions_critical_c : natural := 8;

----

----

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| Memory access | `I/E` | `lb` `lh` `lw` `lbu` `lhu` `sb` `sh` `sw` | 4 + ML

| Memory access | `I/E` | `lb` `lh` `lw` `lbu` `lhu` `sb` `sh` `sw` | 4 + ML

| Memory access | `C`   | `c.lw` `c.sw` `c.lwsp` `c.swsp`           | 4 + ML

| Memory access | `C`   | `c.lw` `c.sw` `c.lwsp` `c.swsp`           | 4 + ML

| Memory access | `A`   | `lr.w` `sc.w`                             | 4 + ML

| Memory access | `A`   | `lr.w` `sc.w`                             | 4 + ML

| Multiplication | `M`  | `mul` `mulh` `mulhsu` `mulhu` | 2+32+2; FAST_MULfootnote:[DSP-based multiplication; enabled via `FAST_MUL_EN`.]: 4

| Multiplication | `M`  | `mul` `mulh` `mulhsu` `mulhu` | 2+32+2; FAST_MULfootnote:[DSP-based multiplication; enabled via `FAST_MUL_EN`.]: 4

| Division       | `M`  | `div` `divu` `rem` `remu`     | 2+32+2

| Division       | `M`  | `div` `divu` `rem` `remu`     | 2+32+2

| System | `I/E` | `fence` | 3

| System | `I/E` | `fence` | 3

| System | `Zifencei` | `fence.i` | 3 + ML

| System | `Zifencei` | `fence.i` | 3 + ML

| Floating-point - artihmetic | `Zfinx` | `fadd.s` | 110

| Floating-point - artihmetic | `Zfinx` | `fadd.s` | 110

| Floating-point - artihmetic | `Zfinx` | `fsub.s` | 112

| Floating-point - artihmetic | `Zfinx` | `fsub.s` | 112

| Floating-point - artihmetic | `Zfinx` | `fmul.s` | 22

| Floating-point - artihmetic | `Zfinx` | `fmul.s` | 22

| Floating-point - compare | `Zfinx` | `fmin.s` `fmax.s` `feq.s` `flt.s` `fle.s` | 13

| Floating-point - compare | `Zfinx` | `fmin.s` `fmax.s` `feq.s` `flt.s` `fle.s` | 13

| Bit-manipulation - shifts | `B(Zbb)` | `cpop` | 3 + 32

| Bit-manipulation - shifts | `B(Zbb)` | `cpop` | 3 + 32

| Bit-manipulation - shifts | `B(Zbb)` | `rol` `ror` `rori` | 3 + SA

| Bit-manipulation - shifts | `B(Zbb)` | `rol` `ror` `rori` | 3 + SA

| Bit-manipulation - single-bit  | `B(Zbs)` | `sbset[i]` `sbclr[i]` `sbinv[i]` `sbext[i]` | 3

| Bit-manipulation - single-bit  | `B(Zbs)` | `sbset[i]` `sbclr[i]` `sbinv[i]` `sbext[i]` | 3

| Bit-manipulation - shifted-add | `B(Zba)` | `sh1add` `sh2add` `sh3add` | 3

| Bit-manipulation - shifted-add | `B(Zba)` | `sh1add` `sh2add` `sh3add` | 3

| Bit-manipulation - carry-less multiply | `B(Zbc)` | `clmul` `clmulh` `clmulr` | 3 + 32

| Bit-manipulation - carry-less multiply | `B(Zbc)` | `clmul` `clmulh` `clmulr` | 3 + 32

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[NOTE]

[NOTE]

The presented values of the *floating-point execution cycles* are average values - obtained from

The presented values of the *floating-point execution cycles* are average values - obtained from

4096 instruction executions using pseudo-random input values. The execution time for emulating the

4096 instruction executions using pseudo-random input values. The execution time for emulating the

until it is explicitly acknowledged by the CPU software (for example by writing to a specific memory-mapped register).

until it is explicitly acknowledged by the CPU software (for example by writing to a specific memory-mapped register).

.Interrupt Signal Requirements - Fast Interrupt Requests

.Interrupt Signal Requirements - Fast Interrupt Requests

[IMPORTANT]

[IMPORTANT]

The NEORV32-specific FIRQ request lines are triggered by a one-shot high-level (i.e. rising edge). Each request is buffered in the CPU control

The NEORV32-specific FIRQ request lines are triggered by a one-shot high-level (i.e. rising edge). Each request is buffered in the CPU control

.Instruction Atomicity

.Instruction Atomicity

[NOTE]

[NOTE]

All instructions execute as atomic operations - interrupts can only trigger _between_ two instructions.

All instructions execute as atomic operations - interrupts can only trigger _between_ two instructions.

So even if there is a permanent interrupt request, exactly one instruction from the interrupt program will be executed before

So even if there is a permanent interrupt request, exactly one instruction from the interrupt program will be executed before

another interrupt handler can start. This allows program progress even if there are permanent interrupt requests.

another interrupt handler can start. This allows program progress even if there are permanent interrupt requests.

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If a load operation causes any exception, the instruction's destination register is

If a load operation causes any exception, the instruction's destination register is

_not written_ at all. Load exceptions caused by a misalignment or a physical memory protection fault do not

_not written_ at all. Load exceptions caused by a misalignment or a physical memory protection fault do not

trigger a bus/memory read-operation at all. Vice versa, exceptions caused by a store address misalignment or a store physical

trigger a bus/memory read-operation at all. Vice versa, exceptions caused by a store address misalignment or a store physical

memory protection fault do not trigger a bus/memory write-operation at all.

memory protection fault do not trigger a bus/memory write-operation at all.

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As a custom extension, the NEORV32 CPU features 16 fast interrupt request (FIRQ) lines via the `firq_i` CPU top

As a custom extension, the NEORV32 CPU features 16 fast interrupt request (FIRQ) lines via the `firq_i` CPU top

entity signals. These interrupts have custom configuration and status flags in the <<_mie>> and <<_mip>> CSRs and also

entity signals. These interrupts have custom configuration and status flags in the <<_mie>> and <<_mip>> CSRs and also

provide custom trap codes in <<_mcause>>. These FIRQs are reserved for NEORV32 processor-internal usage only.

provide custom trap codes in <<_mcause>>. These FIRQs are reserved for NEORV32 processor-internal usage only.

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The following table shows all traps that are currently supported by the NEORV32 CPU. It also shows the prioritization

The following table shows all traps that are currently supported by the NEORV32 CPU. It also shows the prioritization

and the CSR side-effects. A more detailed description of the actual trap triggering events is provided in a further table.

and the CSR side-effects. A more detailed description of the actual trap triggering events is provided in a further table.

[NOTE]

[NOTE]

**Table Annotations**

**Table Annotations**

The "Prio." column shows the priority of each trap. The highest priority is 1. The "`mcause`" column shows the

The "Prio." column shows the priority of each trap. The highest priority is 1. The "`mcause`" column shows the

cause ID of the according trap that is written to <<_mcause>> CSR. The "[RISC-V]" columns show the interrupt/exception code value from the

cause ID of the according trap that is written to <<_mcause>> CSR. The "[RISC-V]" columns show the interrupt/exception code value from the

.NEORV32 Trap Listing

.NEORV32 Trap Listing

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| Prio. | `mcause` | [RISC-V] | ID [C] | Cause | `mepc` | `mtval`

| Prio. | `mcause` | [RISC-V] | ID [C] | Cause | `mepc` | `mtval`

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The following table provides a summarized description of the actual events for triggering a specific trap.

The following table provides a summarized description of the actual events for triggering a specific trap.

.NEORV32 Trap Description

.NEORV32 Trap Description

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| Trap ID [C] | Triggered when ...

| Trap ID [C] | Triggered when ...

| _TRAP_CODE_I_ACCESS_     | bus timeout or bus error during instruction word fetch

| _TRAP_CODE_I_ACCESS_     | bus timeout or bus error during instruction word fetch

| _TRAP_CODE_I_ILLEGAL_    | trying to execute an invalid instruction word (malformed or not supported) or on a privilege violation

| _TRAP_CODE_I_ILLEGAL_    | trying to execute an invalid instruction word (malformed or not supported) or on a privilege violation

| _TRAP_CODE_MENV_CALL_    | executing `ecall` instruction in machine-mode

| _TRAP_CODE_MENV_CALL_    | executing `ecall` instruction in machine-mode

| _TRAP_CODE_UENV_CALL_    | executing `ecall` instruction in user-mode

| _TRAP_CODE_UENV_CALL_    | executing `ecall` instruction in user-mode

| _TRAP_CODE_S_MISALIGNED_ | storing data to an address that is not naturally aligned to the data size (byte, half, word) being stored

| _TRAP_CODE_S_MISALIGNED_ | storing data to an address that is not naturally aligned to the data size (byte, half, word) being stored

| _TRAP_CODE_L_MISALIGNED_ | loading data from an address that is not naturally aligned to the data size  (byte, half, word) being loaded

| _TRAP_CODE_L_MISALIGNED_ | loading data from an address that is not naturally aligned to the data size  (byte, half, word) being loaded

| _TRAP_CODE_S_ACCESS_     | bus timeout or bus error during load data operation

| _TRAP_CODE_S_ACCESS_     | bus timeout or bus error during load data operation

| _TRAP_CODE_L_ACCESS_     | bus timeout or bus error during store data operation

| _TRAP_CODE_L_ACCESS_     | bus timeout or bus error during store data operation

| _TRAP_CODE_FIRQ_0_ ... _TRAP_CODE_FIRQ_15_| caused by interrupt-condition of processor-internal modules, see <<_neorv32_specific_fast_interrupt_requests>>

| _TRAP_CODE_FIRQ_0_ ... _TRAP_CODE_FIRQ_15_| caused by interrupt-condition of processor-internal modules, see <<_neorv32_specific_fast_interrupt_requests>>

completed when the accessed peripheral/memory either sets the `*_bus_ack_i` signal (-> successful completion) or the

completed when the accessed peripheral/memory either sets the `*_bus_ack_i` signal (-> successful completion) or the

`*_bus_err_i` signal (-> failed completion). These bus response signal are also set only for one cycle active.

`*_bus_err_i` signal (-> failed completion). These bus response signal are also set only for one cycle active.

An error indicated by the `*_bus_err_i` signal will raise the according "instruction bus access fault" or

An error indicated by the `*_bus_err_i` signal will raise the according "instruction bus access fault" or

"load/store bus access fault" exception.

"load/store bus access fault" exception.

**Minimal Response Latency**

**Minimal Response Latency**

The transfer can be completed directly in the same cycle as it was initiated (via the `*_bus_re_o` or `*_bus_we_o`

The transfer can be completed directly in the same cycle as it was initiated (via the `*_bus_re_o` or `*_bus_we_o`

signal) if the peripheral sets `*_bus_ack_i` or `*_bus_err_i` high for one cycle. However, in order to shorten the

signal) if the peripheral sets `*_bus_ack_i` or `*_bus_err_i` high for one cycle. However, in order to shorten the

critical path such "asynchronous" completion should be avoided. The default NEORV32 processor-internal modules provide

critical path such "asynchronous" completion should be avoided. The default NEORV32 processor-internal modules provide

exactly **one cycle delay** between initiation and completion of transfers.

exactly **one cycle delay** between initiation and completion of transfers.

**Maximal Response Latency**

**Maximal Response Latency**

Processor-internal peripherals or memories do not have to respond within one cycle after a bus request has been initiated.

Processor-internal peripherals or memories do not have to respond within one cycle after a bus request has been initiated.

However, the bus transaction has to be completed (= acknowledged) within a certain **response time window**. This time window

However, the bus transaction has to be completed (= acknowledged) within a certain **response time window**. This time window

is defined by the global `max_proc_int_response_time_c` constant (default = 15 cycles; processor's VHDL package file `rtl/neorv32_package.vhd`).

is defined by the global `max_proc_int_response_time_c` constant (default = 15 cycles; processor's VHDL package file `rtl/neorv32_package.vhd`).

transfer will time out and raises a **bus fault exception**. The <<_internal_bus_monitor_buskeeper>> keeps track of all _internal_ bus

transfer will time out and raises a **bus fault exception**. The <<_internal_bus_monitor_buskeeper>> keeps track of all _internal_ bus

transactions to enforce this time window.

transactions to enforce this time window.

If any bus operations times out (for example when accessing "address space holes") the BUSKEEPER will issue a bus

If any bus operations times out (for example when accessing "address space holes") the BUSKEEPER will issue a bus

error to the CPU that will raise the according instruction fetch or data access bus exception.

error to the CPU that will raise the according instruction fetch or data access bus exception.

Note that **the bus keeper does not track external accesses via the external memory bus interface**. However,

Note that **the bus keeper does not track external accesses via the external memory bus interface**. However,

the external memory bus interface also provides an _optional_ bus timeout (see section <<_processor_external_memory_interface_wishbone_axi4_lite>>).

the external memory bus interface also provides an _optional_ bus timeout (see section <<_processor_external_memory_interface_wishbone_axi4_lite>>).

**Exemplary Bus Accesses**

**Exemplary Bus Accesses**

.Example bus accesses: see read/write access description below

.Example bus accesses: see read/write access description below

[cols="^2,^2"]

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a| image::cpu_interface_read_long.png[read,300,150]

a| image::cpu_interface_read_long.png[read,300,150]

a| image::cpu_interface_write_long.png[write,300,150]

a| image::cpu_interface_write_long.png[write,300,150]

| Read access | Write access

| Read access | Write access

|=======================

|=======================

**Write Access**

**Write Access**

For a write access, the access address (`bus_addr_o`), the data to be written (`bus_wdata_o`) and the byte

For a write access, the access address (`bus_addr_o`), the data to be written (`bus_wdata_o`) and the byte

enable signals (`bus_ben_o`) are set when bus_we_o goes high. These three signals are kept stable until the

enable signals (`bus_ben_o`) are set when bus_we_o goes high. These three signals are kept stable until the

transaction is completed. In the example the accessed peripheral cannot answer directly in the next

transaction is completed. In the example the accessed peripheral cannot answer directly in the next

cycle after issuing. Here, the transaction is successful and the peripheral sets the `bus_ack_i` signal several

cycle after issuing. Here, the transaction is successful and the peripheral sets the `bus_ack_i` signal several

cycles after issuing.

cycles after issuing.

**Read Access**

**Read Access**

For a read access, the accessed address (`bus_addr_o`) is set when `bus_re_o` goes high. The address is kept

For a read access, the accessed address (`bus_addr_o`) is set when `bus_re_o` goes high. The address is kept

stable until the transaction is completed. In the example the accessed peripheral cannot answer

stable until the transaction is completed. In the example the accessed peripheral cannot answer

directly in the next cycle after issuing. The peripheral hast to apply the read data right in the same cycle as

directly in the next cycle after issuing. The peripheral hast to apply the read data right in the same cycle as

the bus transaction is completed (here, the transaction is successful and the peripheral sets the `bus_ack_i`

the bus transaction is completed (here, the transaction is successful and the peripheral sets the `bus_ack_i`

signal).

signal).

**Access Boundaries**

**Access Boundaries**

The instruction interface will always access memory on word (= 32-bit) boundaries even if fetching

The instruction interface will always access memory on word (= 32-bit) boundaries even if fetching

compressed (16-bit) instructions. The data interface can access memory on byte (= 8-bit), half-word (= 16-

compressed (16-bit) instructions. The data interface can access memory on byte (= 8-bit), half-word (= 16-

bit) and word (= 32-bit) boundaries.

bit) and word (= 32-bit) boundaries.

**Exclusive (Atomic) Access**

**Exclusive (Atomic) Access**

The CPU can access memory in an exclusive manner by generating a load-reservate and store-conditional

The CPU can access memory in an exclusive manner by generating a load-reservate and store-conditional

combination. Normally, these combinations should target the same memory address.

combination. Normally, these combinations should target the same memory address.

[TIP]

[TIP]

For more information regarding the SoC-level behavior and requirements of atomic operations see

For more information regarding the SoC-level behavior and requirements of atomic operations see

section <<_processor_external_memory_interface_wishbone_axi4_lite>>.

section <<_processor_external_memory_interface_wishbone_axi4_lite>>.

**Memory Barriers**

**Memory Barriers**

Whenever the CPU executes a _fence_ instruction, the according interface signal is set high for one cycle

Whenever the CPU executes a _fence_ instruction, the according interface signal is set high for one cycle

(`d_bus_fence_o` for a `fence` instruction; `i_bus_fence_o` for a `fencei` instruction). It is the task of the

(`d_bus_fence_o` for a `fence` instruction; `i_bus_fence_o` for a `fencei` instruction). It is the task of the

memory system to perform the necessary operations (for example a cache flush and refill).

memory system to perform the necessary operations (for example a cache flush and refill).

In order to reduce routing constraints (and by this the actual hardware requirements), most uncritical

In order to reduce routing constraints (and by this the actual hardware requirements), most uncritical

registers of the NEORV32 CPU as well as most register of the whole NEORV32 Processor do not use **a

registers of the NEORV32 CPU as well as most register of the whole NEORV32 Processor do not use **a

dedicated hardware reset**. "Uncritical registers" in this context means that the initial value of these registers

dedicated hardware reset**. "Uncritical registers" in this context means that the initial value of these registers

after power-up is not relevant for a defined CPU boot process.

after power-up is not relevant for a defined CPU boot process.

**Rationale**

**Rationale**

A good example to illustrate the concept of uncritical registers is a pipelined processing engine. Each stage

A good example to illustrate the concept of uncritical registers is a pipelined processing engine. Each stage

of the engine features an N-bit _data register_ and a 1-bit _status register_. The status register is set when the

of the engine features an N-bit _data register_ and a 1-bit _status register_. The status register is set when the

data in the according data register is valid. At the end of the pipeline the status register might trigger a write-back

data in the according data register is valid. At the end of the pipeline the status register might trigger a write-back

irrelevant as long as the status registers are all reset to a defined value that indicates there is no valid data in

irrelevant as long as the status registers are all reset to a defined value that indicates there is no valid data in

the pipeline's data register. Therefore, the pipeline data register do no require a dedicated reset as they do not

the pipeline's data register. Therefore, the pipeline data register do no require a dedicated reset as they do not

control the actual operation (in contrast to the status register). This makes the pipeline data registers from

control the actual operation (in contrast to the status register). This makes the pipeline data registers from

this example "uncritical registers".

this example "uncritical registers".

**NEORV32 CPU Reset**

**NEORV32 CPU Reset**

In terms of the NEORV32 CPU, there are several pipeline registers, state machine registers and even status

In terms of the NEORV32 CPU, there are several pipeline registers, state machine registers and even status

and control registers (CSRs) that do not require a defined initial state to ensure a correct boot process. The

and control registers (CSRs) that do not require a defined initial state to ensure a correct boot process. The

pipeline register will get initialized by the CPU's internal state machines, which are initialized from the main

pipeline register will get initialized by the CPU's internal state machines, which are initialized from the main

the lack of dedicated hardware resets of certain CSRs. For example the machine interrupt-enable CSR <<_mie>>

the lack of dedicated hardware resets of certain CSRs. For example the machine interrupt-enable CSR <<_mie>>

does not provide a dedicated reset. The value after reset of this register is uncritical as interrupts cannot fire

does not provide a dedicated reset. The value after reset of this register is uncritical as interrupts cannot fire

because the global interrupt enabled flag in the status register (`mstatsus(mie)`) _do_ provide a dedicated

because the global interrupt enabled flag in the status register (`mstatsus(mie)`) _do_ provide a dedicated

hardware reset setting this bit to low (globally disabling interrupts).

hardware reset setting this bit to low (globally disabling interrupts).

**Reset Configuration**

**Reset Configuration**

Most CPU-internal register do provide an asynchronous reset in the VHDL code, but the "don't care" value

Most CPU-internal register do provide an asynchronous reset in the VHDL code, but the "don't care" value

(VHDL `'-'`) is used for initialization of all uncritical registers, effectively generating a flip-flop without a

(VHDL `'-'`) is used for initialization of all uncritical registers, effectively generating a flip-flop without a

reset. However, certain applications or situations (like advanced gate-level / timing simulations) might

reset. However, certain applications or situations (like advanced gate-level / timing simulations) might

----

----

-- use dedicated hardware reset value for UNCRITICAL registers --

-- use dedicated hardware reset value for UNCRITICAL registers --

-- FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value

-- FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value

constant dedicated_reset_c : boolean := false;

constant dedicated_reset_c : boolean := false;

----

----