| Line 67... |
Line 67... |
6+^| **<<_floating_point_csrs>>**
|
6+^| **<<_floating_point_csrs>>**
|
| 0x001 | <<_fflags>> | _CSR_FFLAGS_ | r/w | Floating-point accrued exceptions |
|
| 0x001 | <<_fflags>> | _CSR_FFLAGS_ | r/w | Floating-point accrued exceptions |
|
| 0x002 | <<_frm>> | _CSR_FRM_ | r/w | Floating-point dynamic rounding mode |
|
| 0x002 | <<_frm>> | _CSR_FRM_ | r/w | Floating-point dynamic rounding mode |
|
| 0x003 | <<_fcsr>> | _CSR_FCSR_ | r/w | Floating-point control and status (`frm` + `fflags`) |
|
| 0x003 | <<_fcsr>> | _CSR_FCSR_ | r/w | Floating-point control and status (`frm` + `fflags`) |
|
6+^| **<<_machine_trap_setup>>**
|
6+^| **<<_machine_trap_setup>>**
|
| 0x300 | <<_mstatus>> | _CSR_MSTATUS_ | r/w | Machine status register | `C`
|
| 0x300 | <<_mstatus>> | _CSR_MSTATUS_ | r/w | Machine status register - low word | `C`
|
| 0x301 | <<_misa>> | _CSR_MISA_ | r/- | Machine CPU ISA and extensions | `R`
|
| 0x301 | <<_misa>> | _CSR_MISA_ | r/- | Machine CPU ISA and extensions | `R`
|
| 0x304 | <<_mie>> | _CSR_MIE_ | r/w | Machine interrupt enable register | `X`
|
| 0x304 | <<_mie>> | _CSR_MIE_ | r/w | Machine interrupt enable register | `X`
|
| 0x305 | <<_mtvec>> | _CSR_MTVEC_ | r/w | Machine trap-handler base address (for ALL traps) |
|
| 0x305 | <<_mtvec>> | _CSR_MTVEC_ | r/w | Machine trap-handler base address (for ALL traps) |
|
| 0x306 | <<_mcounteren>> | _CSR_MCOUNTEREN_ | r/w | Machine counter-enable register | `C`
|
| 0x306 | <<_mcounteren>> | _CSR_MCOUNTEREN_ | r/w | Machine counter-enable register | `C`
|
|
| 0x310 | <<_mstatush>> | _CSR_MSTATUSH_ | r/- | Machine status register - high word | `C`
|
6+^| **<<_machine_trap_handling>>**
|
6+^| **<<_machine_trap_handling>>**
|
| 0x340 | <<_mscratch>> | _CSR_MSCRATCH_ | r/w | Machine scratch register |
|
| 0x340 | <<_mscratch>> | _CSR_MSCRATCH_ | r/w | Machine scratch register |
|
| 0x341 | <<_mepc>> | _CSR_MEPC_ | r/w | Machine exception program counter |
|
| 0x341 | <<_mepc>> | _CSR_MEPC_ | r/w | Machine exception program counter |
|
| 0x342 | <<_mcause>> | _CSR_MCAUSE_ | r/w | Machine trap cause | `X`
|
| 0x342 | <<_mcause>> | _CSR_MCAUSE_ | r/w | Machine trap cause | `X`
|
| 0x343 | <<_mtval>> | _CSR_MTVAL_ | r/- | Machine bad address or instruction | `R`
|
| 0x343 | <<_mtval>> | _CSR_MTVAL_ | r/- | Machine bad address or instruction | `R`
|
| Line 83... |
Line 84... |
6+^| **<<_machine_physical_memory_protection>>**
|
6+^| **<<_machine_physical_memory_protection>>**
|
| 0x3a0 .. 0x3af | <<_pmpcfg, `pmpcfg0`>> .. <<_pmpcfg, `pmpcfg15`>> | _CSR_PMPCFG0_ .. _CSR_PMPCFG15_ | r/w | Physical memory protection config. for region 0..63 | `C`
|
| 0x3a0 .. 0x3af | <<_pmpcfg, `pmpcfg0`>> .. <<_pmpcfg, `pmpcfg15`>> | _CSR_PMPCFG0_ .. _CSR_PMPCFG15_ | r/w | Physical memory protection config. for region 0..63 | `C`
|
| 0x3b0 .. 0x3ef | <<_pmpaddr, `pmpaddr0`>> .. <<_pmpaddr, `pmpaddr63`>> | _CSR_PMPADDR0_ .. _CSR_PMPADDR63_ | r/w | Physical memory protection addr. register region 0..63 |
|
| 0x3b0 .. 0x3ef | <<_pmpaddr, `pmpaddr0`>> .. <<_pmpaddr, `pmpaddr63`>> | _CSR_PMPADDR0_ .. _CSR_PMPADDR63_ | r/w | Physical memory protection addr. register region 0..63 |
|
6+^| **<<_machine_counters_and_timers>>**
|
6+^| **<<_machine_counters_and_timers>>**
|
| 0xb00 | <<_mcycleh, `mcycle`>> | _CSR_MCYCLE_ | r/w | Machine cycle counter low word |
|
| 0xb00 | <<_mcycleh, `mcycle`>> | _CSR_MCYCLE_ | r/w | Machine cycle counter low word |
|
| 0xb02 | <<_minstreth, `_minstret`>> | _CSR_MINSTRET_ | r/w | Machine instruction-retired counter low word |
|
| 0xb02 | <<_minstreth, `minstret`>> | _CSR_MINSTRET_ | r/w | Machine instruction-retired counter low word |
|
| 0xb80 | <<_mcycleh>> | _CSR_MCYCLE_ | r/w | Machine cycle counter high word |
|
| 0xb80 | <<_mcycleh>> | _CSR_MCYCLE_ | r/w | Machine cycle counter high word |
|
| 0xb82 | <<_minstreth>> | _CSR_MINSTRET_ | r/w | Machine instruction-retired counter high word |
|
| 0xb82 | <<_minstreth>> | _CSR_MINSTRET_ | r/w | Machine instruction-retired counter high word |
|
| 0xc00 | <<_cycleh, `cycle`>> | _CSR_CYCLE_ | r/- | Cycle counter low word |
|
| 0xc00 | <<_cycleh, `cycle`>> | _CSR_CYCLE_ | r/- | Cycle counter low word |
|
| 0xc01 | <<_timeh, `time`>> | _CSR_TIME_ | r/- | System time (from MTIME) low word |
|
| 0xc01 | <<_timeh, `time`>> | _CSR_TIME_ | r/- | System time (from MTIME) low word |
|
| 0xc02 | <<_instreth, `instret`>> | _CSR_INSTRET_ | r/- | Instruction-retired counter low word |
|
| 0xc02 | <<_instreth, `instret`>> | _CSR_INSTRET_ | r/- | Instruction-retired counter low word |
|
| Line 103... |
Line 104... |
6+^| **<<_machine_information_registers>>**
|
6+^| **<<_machine_information_registers>>**
|
| 0xf11 | <<_mvendorid>> | _CSR_MVENDORID_ | r/- | Vendor ID |
|
| 0xf11 | <<_mvendorid>> | _CSR_MVENDORID_ | r/- | Vendor ID |
|
| 0xf12 | <<_marchid>> | _CSR_MARCHID_ | r/- | Architecture ID |
|
| 0xf12 | <<_marchid>> | _CSR_MARCHID_ | r/- | Architecture ID |
|
| 0xf13 | <<_mimpid>> | _CSR_MIMPID_ | r/- | Machine implementation ID / version |
|
| 0xf13 | <<_mimpid>> | _CSR_MIMPID_ | r/- | Machine implementation ID / version |
|
| 0xf14 | <<_mhartid>> | _CSR_MHARTID_ | r/- | Machine thread ID |
|
| 0xf14 | <<_mhartid>> | _CSR_MHARTID_ | r/- | Machine thread ID |
|
|
| 0xf15 | <<_mconfigptr>> | _CSR_MCONFIGPTR_ | r/- | Machine configuration pointer register |
|
6+^| **<<_neorv32_specific_custom_csrs>>**
|
6+^| **<<_neorv32_specific_custom_csrs>>**
|
| 0xfc0 | <<_mzext>> | _CSR_MZEXT_ | r/- | Available `Z*` CPU extensions |
|
| 0xfc0 | <<_mzext>> | _CSR_MZEXT_ | r/- | Available `Z*` CPU extensions |
|
|=======================
|
|=======================
|
|
|
|
|
| Line 182... |
Line 184... |
.Machine status register
|
.Machine status register
|
[cols="^1,<3,^1,<5"]
|
[cols="^1,<3,^1,<5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Bit | Name [C] | R/W | Function
|
| Bit | Name [C] | R/W | Function
|
|
| 31 | _CSR_MSTATUS_SD_ | r/- | Read-only bit that is set if the FS field is not all-zero (state _OFF_)
|
|
| 21 | _CSR_MSTATUS_TW_ | r/w | Timeout wait: raise illegal instruction exception if `WFI` instruction is executed outside of M-mode when set
|
|
| 14:13 | _CSR_MSTATUS_FS_H_ : _CSR_MSTATUS_FS_L_ | r/w | Floating-point extension state; `00` = _OFF_, `11` = _DIRTY_; writing any other value will
|
|
always set _DIRTY_; if `FS` is _off_ all FPU instructions and FPU CSR access will raise an illegal instruction exception; these status bits are hardwired
|
|
to zero if no FPU is present (_CPU_MZEXT_ZFINX_ = false)
|
| 12:11 | _CSR_MSTATUS_MPP_H_ : _CSR_MSTATUS_MPP_L_ | r/w | Previous machine privilege level, 11 = machine (M) level, 00 = user (U) level
|
| 12:11 | _CSR_MSTATUS_MPP_H_ : _CSR_MSTATUS_MPP_L_ | r/w | Previous machine privilege level, 11 = machine (M) level, 00 = user (U) level
|
| 7 | _CSR_MSTATUS_MPIE_ | r/w | Previous machine global interrupt enable flag state
|
| 7 | _CSR_MSTATUS_MPIE_ | r/w | Previous machine global interrupt enable flag state
|
| 3 | _CSR_MSTATUS_MIE_ | r/w | Machine global interrupt enable flag
|
| 3 | _CSR_MSTATUS_MIE_ | r/w | Machine global interrupt enable flag
|
|=======================
|
|=======================
|
|
|
| Line 296... |
Line 303... |
.Machine counter enable register
|
.Machine counter enable register
|
[cols="^1,<3,^1,<5"]
|
[cols="^1,<3,^1,<5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Bit | Name [C] | R/W | Function
|
| Bit | Name [C] | R/W | Function
|
| 31:16 | - | r/- | User-level code is **not** allowed to read HPM counter
|
| 31:16 | `0` | r/- | Always zero: user-level code is **not** allowed to read HPM counters
|
| 2 | _CSR_MCOUNTEREN_IR_ | r/w | User-level code is allowed to read `cycle[h]` CSRs when set
|
| 2 | _CSR_MCOUNTEREN_IR_ | r/w | User-level code is allowed to read `cycle[h]` CSRs when set
|
| 1 | _CSR_MCOUNTEREN_TM_ | r/w | User-level code is allowed to read `time[h]` CSRs when set
|
| 1 | _CSR_MCOUNTEREN_TM_ | r/w | User-level code is allowed to read `time[h]` CSRs when set
|
| 0 | _CSR_MCOUNTEREN_CY_ | r/w | User-level code is allowed to read `instret[h]` CSRs when set
|
| 0 | _CSR_MCOUNTEREN_CY_ | r/w | User-level code is allowed to read `instret[h]` CSRs when set
|
|=======================
|
|=======================
|
|
|
|
|
|
:sectnums!:
|
|
===== **`mstatush`**
|
|
|
|
[cols="4,27,>7"]
|
|
[frame="topbot",grid="none"]
|
|
|======
|
|
| 0x310 | **Machine status register - high word** | `mstatush`
|
|
3+| Reset value: _0x00000000_
|
|
3+| The `mstatush` CSR is compatible to the RISC-V specifications. In combination with <<_mstatus>> it shows additional
|
|
execution state information. The NEORV32 `mstatush` CSR is read-only and all bits are hardwired to zero.
|
|
|======
|
|
|
|
[NOTE]
|
|
The NEORV32 `mstatush` CSR is not a physical register. All write access are ignored and all read accesses will always
|
|
return zero. However, any access will not raise an illegal instruction exception. The CSR address is implemented
|
|
in order to comply with the RISC-V privilege architecture specs.
|
|
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== Machine Trap Handling
|
==== Machine Trap Handling
|
|
|
| Line 604... |
Line 630... |
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|======
|
| 0x232 -0x33f | **Machine hardware performance monitor event selector** | `mhpmevent3` - `mhpmevent31`
|
| 0x232 -0x33f | **Machine hardware performance monitor event selector** | `mhpmevent3` - `mhpmevent31`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `mhpmevent*` CSRs are compatible to the RISC-V specifications. The configuration of these CSR define
|
3+| The `mhpmevent*` CSRs are compatible to the RISC-V specifications. The configuration of these CSR define
|
the architectural events that cause the according `[m]hpmcounter*[h]` counters to increment. All available events are
|
the architectural events that cause the according `mhpmcounter*[h]` counters to increment. All available events are
|
listed in the table below. If more than one event is selected, the according counter will increment if any of
|
listed in the table below. If more than one event is selected, the according counter will increment if any of
|
the enabled events is observed (logical OR). Note that the counter will only increment by 1 step per clock
|
the enabled events is observed (logical OR). Note that the counter will only increment by 1 step per clock
|
cycle even if more than one event is observed. If the CPU is in sleep mode, no HPM counter will increment
|
cycle even if more than one event is observed. If the CPU is in sleep mode, no HPM counter will increment
|
at all.
|
at all.
|
|======
|
|======
|
|
|
The available hardware performance logic is configured via the _HPM_NUM_CNTS_ top entity generic.
|
The available hardware performance logic is configured via the _HPM_NUM_CNTS_ top entity generic.
|
_HPM_NUM_CNTS_ defines the number of implemented performance monitors and thus, the availability of the
|
_HPM_NUM_CNTS_ defines the number of implemented performance monitors and thus, the availability of the
|
according `[m]hpmcounter*[h]` and `mhpmevent*` CSRs.
|
according `mhpmcounter*[h]` and `mhpmevent*` CSRs.
|
|
|
.HPM event selector
|
.HPM event selector
|
[cols="^1,<3,^1,<5"]
|
[cols="^1,<3,^1,<5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Line 679... |
Line 705... |
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Bit | Name [C] | R/W | Event
|
| Bit | Name [C] | R/W | Event
|
| 0 | _CSR_MCOUNTINHIBIT_IR_ | r/w | the `[m]instret[h]` CSRs will auto-increment with each committed instruction when set
|
| 0 | _CSR_MCOUNTINHIBIT_IR_ | r/w | the `[m]instret[h]` CSRs will auto-increment with each committed instruction when set
|
| 2 | _CSR_MCOUNTINHIBIT_IR_ | r/w | the `[m]cycle[h]` CSRs will auto-increment with each clock cycle (if CPU is not in sleep state) when set
|
| 2 | _CSR_MCOUNTINHIBIT_IR_ | r/w | the `[m]cycle[h]` CSRs will auto-increment with each clock cycle (if CPU is not in sleep state) when set
|
| 3:31 | _CSR_MCOUNTINHIBIT_HPM3_ _: _CSR_MCOUNTINHIBIT_HPM31_ | r/w | the `[m]hpmcount*[h]` CSRs will auto-increment according to the configured `mhpmevent*` selector
|
| 3:31 | _CSR_MCOUNTINHIBIT_HPM3_ _: _CSR_MCOUNTINHIBIT_HPM31_ | r/w | the `mhpmcount*[h]` CSRs will auto-increment according to the configured `mhpmevent*` selector
|
|=======================
|
|=======================
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== Machine Information Registers
|
==== Machine Information Registers
|
|
|
|
[NOTE]
|
|
All machine information registers can only be accessed in machine mode and are read-only.
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`mvendorid`**
|
===== **`mvendorid`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
| Line 740... |
Line 768... |
3+| The `mhartid` CSR is compatible to the RISC-V specifications. It is read-only and shows the core's hart ID,
|
3+| The `mhartid` CSR is compatible to the RISC-V specifications. It is read-only and shows the core's hart ID,
|
which is assigned via the CPU's _HW_THREAD_ID_ generic.
|
which is assigned via the CPU's _HW_THREAD_ID_ generic.
|
|======
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== **`mconfigptr`**
|
|
|
|
[cols="4,27,>7"]
|
|
[frame="topbot",grid="none"]
|
|
|======
|
|
| 0xf15 | **Machine configuration pointer register** | `mconfigptr`
|
|
3+| Reset value: `0x00000000`
|
|
3+| This register holds a physical address (if not zero) that points to the base address of an architecture configuration structure.
|
|
Software can traverse this data structure to discover information about the harts, the platform, and their configuration.
|
|
**NOTE: Not assigned yet.**
|
|
|======
|
|
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== NEORV32-Specific Custom CSRs
|
==== NEORV32-Specific Custom CSRs
|
