| Line 66... |
Line 66... |
| Address | Name [ASM] | Name [C] | R/W | Function | Note
|
| Address | Name [ASM] | Name [C] | R/W | Function | Note
|
6+^| **<<_floating_point_csrs>>**
|
6+^| **<<_floating_point_csrs>>**
|
| 0x001 | <<_fflags>> | _CSR_FFLAGS_ | r/w | Floating-point accrued exceptions |
|
| 0x001 | <<_fflags>> | _CSR_FFLAGS_ | r/w | Floating-point accrued exceptions |
|
| 0x002 | <<_frm>> | _CSR_FRM_ | r/w | Floating-point dynamic rounding mode |
|
| 0x002 | <<_frm>> | _CSR_FRM_ | r/w | Floating-point dynamic rounding mode |
|
| 0x003 | <<_fcsr>> | _CSR_FCSR_ | r/w | Floating-point control and status (`frm` + `fflags`) |
|
| 0x003 | <<_fcsr>> | _CSR_FCSR_ | r/w | Floating-point control and status (`frm` + `fflags`) |
|
6+^| **<<_machine_configuration>>**
|
6+^| **<<_machine_configuration_csrs>>**
|
| 0x30a | <<_menvcfg>> | _CSR_MENVCFG_ | r/- | Machine environment configuration register - low word | `R`
|
| 0x30a | <<_menvcfg>> | _CSR_MENVCFG_ | r/- | Machine environment configuration register - low word | `R`
|
| 0x31a | <<_menvcfgh>> | _CSR_MENVCFGH_ | r/- | Machine environment configuration register - low word | `R`
|
| 0x31a | <<_menvcfgh>> | _CSR_MENVCFGH_ | r/- | Machine environment configuration register - low word | `R`
|
6+^| **<<_machine_trap_setup>>**
|
6+^| **<<_machine_trap_setup_csrs>>**
|
| 0x300 | <<_mstatus>> | _CSR_MSTATUS_ | r/w | Machine status register - low word | `C`
|
| 0x300 | <<_mstatus>> | _CSR_MSTATUS_ | r/w | Machine status register - low word | `C`
|
| 0x301 | <<_misa>> | _CSR_MISA_ | r/- | Machine CPU ISA and extensions | `R`
|
| 0x301 | <<_misa>> | _CSR_MISA_ | r/- | Machine CPU ISA and extensions | `R`
|
| 0x304 | <<_mie>> | _CSR_MIE_ | r/w | Machine interrupt enable register | `X`
|
| 0x304 | <<_mie>> | _CSR_MIE_ | r/w | Machine interrupt enable register | `X`
|
| 0x305 | <<_mtvec>> | _CSR_MTVEC_ | r/w | Machine trap-handler base address (for ALL traps) |
|
| 0x305 | <<_mtvec>> | _CSR_MTVEC_ | r/w | Machine trap-handler base address (for ALL traps) |
|
| 0x306 | <<_mcounteren>> | _CSR_MCOUNTEREN_ | r/w | Machine counter-enable register | `C`
|
| 0x306 | <<_mcounteren>> | _CSR_MCOUNTEREN_ | r/w | Machine counter-enable register | `C`
|
| 0x310 | <<_mstatush>> | _CSR_MSTATUSH_ | r/- | Machine status register - high word | `C`
|
| 0x310 | <<_mstatush>> | _CSR_MSTATUSH_ | r/- | Machine status register - high word | `C`
|
6+^| **<<_machine_trap_handling>>**
|
6+^| **<<_machine_trap_handling_csrs>>**
|
| 0x340 | <<_mscratch>> | _CSR_MSCRATCH_ | r/w | Machine scratch register |
|
| 0x340 | <<_mscratch>> | _CSR_MSCRATCH_ | r/w | Machine scratch register |
|
| 0x341 | <<_mepc>> | _CSR_MEPC_ | r/w | Machine exception program counter |
|
| 0x341 | <<_mepc>> | _CSR_MEPC_ | r/w | Machine exception program counter |
|
| 0x342 | <<_mcause>> | _CSR_MCAUSE_ | r/w | Machine trap cause | `X`
|
| 0x342 | <<_mcause>> | _CSR_MCAUSE_ | r/w | Machine trap cause | `X`
|
| 0x343 | <<_mtval>> | _CSR_MTVAL_ | r/- | Machine bad address or instruction | `XR`
|
| 0x343 | <<_mtval>> | _CSR_MTVAL_ | r/- | Machine bad address or instruction | `XR`
|
| 0x344 | <<_mip>> | _CSR_MIP_ | r/- | Machine interrupt pending register | `XR`
|
| 0x344 | <<_mip>> | _CSR_MIP_ | r/- | Machine interrupt pending register | `XR`
|
6+^| **<<_machine_physical_memory_protection>>**
|
6+^| **<<_machine_physical_memory_protection_csrs>>**
|
| 0x3a0 .. 0x3af | <<_pmpcfg, `pmpcfg0`>> .. <<_pmpcfg, `pmpcfg15`>> | _CSR_PMPCFG0_ .. _CSR_PMPCFG15_ | r/w | Physical memory protection config. for region 0..63 | `C`
|
| 0x3a0 .. 0x3af | <<_pmpcfg, `pmpcfg0`>> .. <<_pmpcfg, `pmpcfg15`>> | _CSR_PMPCFG0_ .. _CSR_PMPCFG15_ | r/w | Physical memory protection config. for region 0..63 | `C`
|
| 0x3b0 .. 0x3ef | <<_pmpaddr, `pmpaddr0`>> .. <<_pmpaddr, `pmpaddr63`>> | _CSR_PMPADDR0_ .. _CSR_PMPADDR63_ | r/w | Physical memory protection addr. register region 0..63 |
|
| 0x3b0 .. 0x3ef | <<_pmpaddr, `pmpaddr0`>> .. <<_pmpaddr, `pmpaddr63`>> | _CSR_PMPADDR0_ .. _CSR_PMPADDR63_ | r/w | Physical memory protection addr. register region 0..63 |
|
6+^| **<<_machine_counters_and_timers>>**
|
6+^| **<<_machine_counter_and_timer_csrs>>**
|
| 0xb00 | <<_mcycleh, `mcycle`>> | _CSR_MCYCLE_ | r/w | Machine cycle counter low word |
|
| 0xb00 | <<_mcycleh, `mcycle`>> | _CSR_MCYCLE_ | r/w | Machine cycle counter low word |
|
| 0xb02 | <<_minstreth, `minstret`>> | _CSR_MINSTRET_ | r/w | Machine instruction-retired counter low word |
|
| 0xb02 | <<_minstreth, `minstret`>> | _CSR_MINSTRET_ | r/w | Machine instruction-retired counter low word |
|
| 0xb80 | <<_mcycleh>> | _CSR_MCYCLE_ | r/w | Machine cycle counter high word |
|
| 0xb80 | <<_mcycleh>> | _CSR_MCYCLE_ | r/w | Machine cycle counter high word |
|
| 0xb82 | <<_minstreth>> | _CSR_MINSTRET_ | r/w | Machine instruction-retired counter high word |
|
| 0xb82 | <<_minstreth>> | _CSR_MINSTRET_ | r/w | Machine instruction-retired counter high word |
|
| 0xc00 | <<_cycleh, `cycle`>> | _CSR_CYCLE_ | r/- | Cycle counter low word |
|
| 0xc00 | <<_cycleh, `cycle`>> | _CSR_CYCLE_ | r/- | Cycle counter low word |
|
| 0xc01 | <<_timeh, `time`>> | _CSR_TIME_ | r/- | System time (from MTIME) low word |
|
| 0xc01 | <<_timeh, `time`>> | _CSR_TIME_ | r/- | System time (from MTIME) low word |
|
| 0xc02 | <<_instreth, `instret`>> | _CSR_INSTRET_ | r/- | Instruction-retired counter low word |
|
| 0xc02 | <<_instreth, `instret`>> | _CSR_INSTRET_ | r/- | Instruction-retired counter low word |
|
| 0xc80 | <<_cycleh>> | _CSR_CYCLEH_ | r/- | Cycle counter high word |
|
| 0xc80 | <<_cycleh>> | _CSR_CYCLEH_ | r/- | Cycle counter high word |
|
| 0xc81 | <<_timeh>> | _CSR_TIMEH_ | r/- | System time (from MTIME) high word |
|
| 0xc81 | <<_timeh>> | _CSR_TIMEH_ | r/- | System time (from MTIME) high word |
|
| 0xc82 | <<_instreth>> | _CSR_INSTRETH_ | r/- | Instruction-retired counter high word |
|
| 0xc82 | <<_instreth>> | _CSR_INSTRETH_ | r/- | Instruction-retired counter high word |
|
6+^| **<<_hardware_performance_monitors_hpm>>**
|
6+^| **<<_hardware_performance_monitors_hpm_csrs>>**
|
| 0x323 .. 0x33f | <<_mhpmevent, `mhpmevent3`>> .. <<_mhpmevent, `mhpmevent31`>> | _CSR_MHPMEVENT3_ .. _CSR_MHPMEVENT31_ | r/w | Machine performance-monitoring event selector 3..31 | `X`
|
| 0x323 .. 0x33f | <<_mhpmevent, `mhpmevent3`>> .. <<_mhpmevent, `mhpmevent31`>> | _CSR_MHPMEVENT3_ .. _CSR_MHPMEVENT31_ | r/w | Machine performance-monitoring event selector 3..31 | `X`
|
| 0xb03 .. 0xb1f | <<_mhpmcounterh, `mhpmcounter3`>> .. <<_mhpmcounterh, `mhpmcounter31`>> | _CSR_MHPMCOUNTER3_ .. _CSR_MHPMCOUNTER31_ | r/w | Machine performance-monitoring counter 3..31 low word |
|
| 0xb03 .. 0xb1f | <<_mhpmcounterh, `mhpmcounter3`>> .. <<_mhpmcounterh, `mhpmcounter31`>> | _CSR_MHPMCOUNTER3_ .. _CSR_MHPMCOUNTER31_ | r/w | Machine performance-monitoring counter 3..31 low word |
|
| 0xb83 .. 0xb9f | <<_mhpmcounterh, `mhpmcounter3h`>> .. <<_mhpmcounterh, `mhpmcounter31h`>> | _CSR_MHPMCOUNTER3H_ .. _CSR_MHPMCOUNTER31H_ | r/w | Machine performance-monitoring counter 3..31 high word |
|
| 0xb83 .. 0xb9f | <<_mhpmcounterh, `mhpmcounter3h`>> .. <<_mhpmcounterh, `mhpmcounter31h`>> | _CSR_MHPMCOUNTER3H_ .. _CSR_MHPMCOUNTER31H_ | r/w | Machine performance-monitoring counter 3..31 high word |
|
6+^| **<<_machine_counter_setup>>**
|
6+^| **<<_machine_counter_setup_csrs>>**
|
| 0x320 | <<_mcountinhibit>> | _CSR_MCOUNTINHIBIT_ | r/w | Machine counter-enable register |
|
| 0x320 | <<_mcountinhibit>> | _CSR_MCOUNTINHIBIT_ | r/w | Machine counter-enable register |
|
6+^| **<<_machine_information_registers>>**
|
6+^| **<<_machine_information_csrs>>**
|
| 0xf11 | <<_mvendorid>> | _CSR_MVENDORID_ | r/- | Vendor ID |
|
| 0xf11 | <<_mvendorid>> | _CSR_MVENDORID_ | r/- | Vendor ID |
|
| 0xf12 | <<_marchid>> | _CSR_MARCHID_ | r/- | Architecture ID |
|
| 0xf12 | <<_marchid>> | _CSR_MARCHID_ | r/- | Architecture ID |
|
| 0xf13 | <<_mimpid>> | _CSR_MIMPID_ | r/- | Machine implementation ID / version |
|
| 0xf13 | <<_mimpid>> | _CSR_MIMPID_ | r/- | Machine implementation ID / version |
|
| 0xf14 | <<_mhartid>> | _CSR_MHARTID_ | r/- | Machine thread ID |
|
| 0xf14 | <<_mhartid>> | _CSR_MHARTID_ | r/- | Machine thread ID |
|
| 0xf15 | <<_mconfigptr>> | _CSR_MCONFIGPTR_ | r/- | Machine configuration pointer register |
|
| 0xf15 | <<_mconfigptr>> | _CSR_MCONFIGPTR_ | r/- | Machine configuration pointer register |
|
| Line 166... |
Line 166... |
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== Machine Configuration
|
==== Machine Configuration CSRs
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`menvcfg`**
|
===== **`menvcfg`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
| Line 197... |
Line 197... |
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== Machine Trap Setup
|
==== Machine Trap Setup CSRs
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`mstatus`**
|
===== **`mstatus`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
| Line 359... |
Line 359... |
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== Machine Trap Handling
|
==== Machine Trap Handling CSRs
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`mscratch`**
|
===== **`mscratch`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
| Line 445... |
Line 445... |
|======
|
|======
|
| 0x344 | **Machine interrupt Pending** | `mip`
|
| 0x344 | **Machine interrupt Pending** | `mip`
|
3+| Reset value: _0x00000000_
|
3+| Reset value: _0x00000000_
|
3+| The `mip` CSR is compatible to the RISC-V specifications and also provides custom extensions. It shows currently _pending_ interrupts.
|
3+| The `mip` CSR is compatible to the RISC-V specifications and also provides custom extensions. It shows currently _pending_ interrupts.
|
Since this register is read-only, pending interrupts of processor-internal modules can only be cleared by acknowledging the interrupt-causing
|
Since this register is read-only, pending interrupts of processor-internal modules can only be cleared by acknowledging the interrupt-causing
|
device. However, pending interrupts can be ignored by clearing the accordind <<_mie>> register bits.
|
device. However, pending interrupts can be ignored by clearing the according <<_mie>> register bits.
|
The following CSR bits are implemented (all remaining bits are always zero and are read-only).
|
The following CSR bits are implemented (all remaining bits are always zero and are read-only).
|
|======
|
|======
|
|
|
.Machine interrupt pending register
|
.Machine interrupt pending register
|
[cols="^1,<3,^1,<5"]
|
[cols="^1,<3,^1,<5"]
|
| Line 467... |
Line 467... |
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== Machine Physical Memory Protection
|
==== Machine Physical Memory Protection CSRs
|
|
|
The available physical memory protection logic is configured via the _PMP_NUM_REGIONS_ and
|
The available physical memory protection logic is configured via the _PMP_NUM_REGIONS_ and
|
_PMP_MIN_GRANULARITY_ top entity generics. _PMP_NUM_REGIONS_ defines the number of implemented
|
_PMP_MIN_GRANULARITY_ top entity generics. _PMP_NUM_REGIONS_ defines the number of implemented
|
protection regions and thus, the availability of the according `pmpcfg*` and `pmpaddr*` CSRs.
|
protection regions and thus, the availability of the according `pmpcfg*` and `pmpaddr*` CSRs.
|
|
|
| Line 530... |
Line 530... |
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== (Machine) Counters and Timers
|
==== (Machine) Counter and Timer CSRs
|
|
|
|
The (machine) counters and timers are implemented when the `Zicntr` ISA extensions is enabled (default)
|
|
via the <<_cpu_extension_riscv_zicntr>> generic.
|
|
|
[NOTE]
|
[NOTE]
|
The <<_cpu_cnt_width>> generic defines the total size of the CPU's <<_cycleh>> and <<_instreth>>
|
The <<_cpu_cnt_width>> generic defines the total size of the CPU's <<_cycleh>> and <<_instreth>>
|
/ <<_mcycleh>> and <<_minstreth>>
|
/ <<_mcycleh>> and <<_minstreth>>
|
counter CSRs (low and high words combined); the time CSRs are not affected by this generic. Note that any
|
counter CSRs (low and high words combined); the time CSRs are not affected by this generic. Note that any
|
| Line 551... |
Line 554... |
and any write access to them is ignored. Furthermore, the according MSBs of `[m]cycle` and `[m]instret` are read-only
|
and any write access to them is ignored. Furthermore, the according MSBs of `[m]cycle` and `[m]instret` are read-only
|
and always read as zero. This configuration will also set the _SYSINFO_CPU_ZXSCNT_ flag ("small counters") in
|
and always read as zero. This configuration will also set the _SYSINFO_CPU_ZXSCNT_ flag ("small counters") in
|
the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +
|
the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +
|
+
|
+
|
If _CPU_CNT_WIDTH_ is 0, the <<_cycleh>> and <<_instreth>> / <<_mcycleh>> and <<_minstreth>> CSRs are hardwired to zero
|
If _CPU_CNT_WIDTH_ is 0, the <<_cycleh>> and <<_instreth>> / <<_mcycleh>> and <<_minstreth>> CSRs are hardwired to zero
|
and any write access to them is ignored. This configuration will also set the _SYSINFO_CPU_ZXNOCNT_ flag ("no counters") in the
|
and any write access to them is ignored.
|
`CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
|
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`cycle[h]`**
|
===== **`cycle[h]`**
|
|
|
| Line 631... |
Line 633... |
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== Hardware Performance Monitors (HPM)
|
==== Hardware Performance Monitors (HPM) CSRs
|
|
|
The available hardware performance logic is configured via the <<_hpm_num_cnts>> top entity generic,
|
|
which defines the number of implemented performance monitors and thus, the availability of the
|
|
according `mhpmcounter*[h]` and `mhpmevent*` CSRs.
|
|
|
|
[IMPORTANT]
|
The hardware performance monitor CSRs are implemented when the `Zihpm` ISA extension is enabled via the
|
The HPM system only implements machine-mode access. Hence, `hpmcounter*[h]` CSR are not implemented
|
<<_cpu_extension_riscv_zihpm>> generic.
|
and any access (even) from machine mode will raise an exception. Furthermore, the according bits of <<_mcounteren>>
|
|
used to configure user-mode access to `hpmcounter*[h]` are hard-wired to zero.
|
|
|
|
The total counter size of the HPMs can be configured before synthesis via the <<_hpm_cnt_width>> generic (0..64-bit).
|
The actually implemented hardware performance logic is configured via the <<_hpm_num_cnts>> top entity generic,
|
|
which defines the number of implemented performance monitors. Note that always all 28 HPM counter and configuration registers
|
|
(`mhpmcounter*[h]` and `mhpmevent*`) are implemented, but only the actually configured ones are real registers and
|
|
not hardwired to zero.
|
|
|
[TIP]
|
[TIP]
|
If trying to access an HPM-related CSR beyond <<_hpm_num_cnts>> **no illegal instruction exception is
|
If trying to access an HPM-related CSR beyond <<_hpm_num_cnts>> **no illegal instruction exception is
|
triggered**. The according CSRs are read-only (writes are ignored) and always return zero.
|
triggered**. The according CSRs are read-only (writes are ignored) and always return zero.
|
|
|
|
[IMPORTANT]
|
|
The HPM system only allows machine-mode access. Hence, `hpmcounter*[h]` CSR are not implemented
|
|
and any access (even) from machine mode will raise an exception. Furthermore, the according bits of <<_mcounteren>>
|
|
used to configure user-mode access to `hpmcounter*[h]` are hard-wired to zero.
|
|
|
|
The total counter width of the HPMs can be configured before synthesis via the <<_hpm_cnt_width>> generic (0..64-bit).
|
|
|
[NOTE]
|
[NOTE]
|
The total LSB-aligned HPM counter size (low word CSR + high word CSR) is defined via the
|
The total LSB-aligned HPM counter size (low word CSR + high word CSR) is defined via the
|
<<_hpm_num_cnts>> generic (0..64-bit). If <<_hpm_num_cnts>> is less than 64, all unused MSB-aligned
|
<<_hpm_num_cnts>> generic (0..64-bit). If <<_hpm_num_cnts>> is less than 64, all unused MSB-aligned
|
bits are hardwired to zero.
|
bits are hardwired to zero.
|
|
|
| Line 715... |
Line 721... |
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== Machine Counter Setup
|
==== Machine Counter Setup CSRs
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`mcountinhibit`**
|
===== **`mcountinhibit`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
| Line 745... |
Line 751... |
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== Machine Information Registers
|
==== Machine Information CSRs
|
|
|
[NOTE]
|
[NOTE]
|
All machine information registers can only be accessed in machine mode and are read-only.
|
All machine information registers can only be accessed in machine mode and are read-only.
|
|
|
:sectnums!:
|
:sectnums!:
|
