| Line 58... |
Line 58... |
* `X`: _custom_ - have or are a custom CPU-specific extension (that is allowed by the RISC-V specs)
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* `X`: _custom_ - have or are a custom CPU-specific extension (that is allowed by the RISC-V specs)
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* `R`: _read-only_ - are read-only (in contrast to the originally specified r/w capability)
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* `R`: _read-only_ - are read-only (in contrast to the originally specified r/w capability)
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* `C`: _constrained_ - have a constrained compatibility, not all specified bits are implemented
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* `C`: _constrained_ - have a constrained compatibility, not all specified bits are implemented
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.NEORV32 Control and Status Registers (CSRs)
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.NEORV32 Control and Status Registers (CSRs)
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[cols="<4,<7,<10,^3,<11,^3"]
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[cols="<6,<11,<16,^3,<25,^3"]
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[options="header"]
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[options="header"]
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|=======================
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|=======================
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| Address | Name [ASM] | Name [C] | R/W | Function | Note
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| Address | Name [ASM] | Name [C] | R/W | Function | Note
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6+^| **<<_floating_point_csrs>>**
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6+^| **<<_floating_point_csrs>>**
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| 0x001 | <<_fflags>> | _CSR_FFLAGS_ | r/w | Floating-point accrued exceptions |
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| 0x001 | <<_fflags>> | _CSR_FFLAGS_ | r/w | Floating-point accrued exceptions |
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| Line 80... |
Line 80... |
| 0x310 | <<_mstatush>> | _CSR_MSTATUSH_ | r/- | Machine status register - high word | `C`
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| 0x310 | <<_mstatush>> | _CSR_MSTATUSH_ | r/- | Machine status register - high word | `C`
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6+^| **<<_machine_trap_handling_csrs>>**
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6+^| **<<_machine_trap_handling_csrs>>**
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| 0x340 | <<_mscratch>> | _CSR_MSCRATCH_ | r/w | Machine scratch register |
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| 0x340 | <<_mscratch>> | _CSR_MSCRATCH_ | r/w | Machine scratch register |
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| 0x341 | <<_mepc>> | _CSR_MEPC_ | r/w | Machine exception program counter |
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| 0x341 | <<_mepc>> | _CSR_MEPC_ | r/w | Machine exception program counter |
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| 0x342 | <<_mcause>> | _CSR_MCAUSE_ | r/w | Machine trap cause | `X`
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| 0x342 | <<_mcause>> | _CSR_MCAUSE_ | r/w | Machine trap cause | `X`
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| 0x343 | <<_mtval>> | _CSR_MTVAL_ | r/- | Machine bad address or instruction | `XR`
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| 0x343 | <<_mtval>> | _CSR_MTVAL_ | r/- | Machine bad address or instruction | `R`
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| 0x344 | <<_mip>> | _CSR_MIP_ | r/- | Machine interrupt pending register | `XR`
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| 0x344 | <<_mip>> | _CSR_MIP_ | r/w | Machine interrupt pending register | `X`
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6+^| **<<_machine_physical_memory_protection_csrs>>**
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6+^| **<<_machine_physical_memory_protection_csrs>>**
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| 0x3a0 .. 0x3af | <<_pmpcfg, `pmpcfg0`>> .. <<_pmpcfg, `pmpcfg15`>> | _CSR_PMPCFG0_ .. _CSR_PMPCFG15_ | r/w | Physical memory protection config. for region 0..63 | `C`
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| 0x3a0 .. 0x3af | <<_pmpcfg, `pmpcfg0`>> .. <<_pmpcfg, `pmpcfg15`>> | _CSR_PMPCFG0_ .. _CSR_PMPCFG15_ | r/w | Physical memory protection config. for region 0..63 | `C`
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| 0x3b0 .. 0x3ef | <<_pmpaddr, `pmpaddr0`>> .. <<_pmpaddr, `pmpaddr63`>> | _CSR_PMPADDR0_ .. _CSR_PMPADDR63_ | r/w | Physical memory protection addr. register region 0..63 |
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| 0x3b0 .. 0x3ef | <<_pmpaddr, `pmpaddr0`>> .. <<_pmpaddr, `pmpaddr63`>> | _CSR_PMPADDR0_ .. _CSR_PMPADDR63_ | r/w | Physical memory protection addr. register region 0..63 |
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6+^| **<<_machine_counter_and_timer_csrs>>**
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6+^| **<<_machine_counter_and_timer_csrs>>**
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| 0xb00 | <<_mcycleh, `mcycle`>> | _CSR_MCYCLE_ | r/w | Machine cycle counter low word |
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| 0xb00 | <<_mcycleh, `mcycle`>> | _CSR_MCYCLE_ | r/w | Machine cycle counter low word |
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| Line 444... |
Line 444... |
[frame="topbot",grid="none"]
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[frame="topbot",grid="none"]
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|======
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|======
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| 0x344 | **Machine interrupt Pending** | `mip`
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| 0x344 | **Machine interrupt Pending** | `mip`
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3+| Reset value: _0x00000000_
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3+| Reset value: _0x00000000_
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3+| The `mip` CSR is compatible to the RISC-V specifications and also provides custom extensions. It shows currently _pending_ interrupts.
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3+| The `mip` CSR is compatible to the RISC-V specifications and also provides custom extensions. It shows currently _pending_ interrupts.
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Since this register is read-only, pending interrupts of processor-internal modules can only be cleared by acknowledging the interrupt-causing
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The bits for the standard RISC-V interrupts are read-only. Hence, these interrupts cannot be cleared using the `mip` register and must
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device. However, pending interrupts can be ignored by clearing the according <<_mie>> register bits.
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be cleared/acknowledged within the according interrupt-generating device.
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The following CSR bits are implemented (all remaining bits are always zero and are read-only).
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The upper 16 bits represent the status of the CPU's fast interrupt request lines (FIRQ). Once triggered, these _have to be cleared_ again by setting
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the according `mip` bit in the interrupt handler routine to clear the current interrupt request.
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|======
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|======
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.Machine interrupt pending register
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.Machine interrupt pending register
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[cols="^1,<3,^1,<5"]
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[cols="^1,<3,^1,<5"]
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
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| Bit | Name [C] | R/W | Function
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| Bit | Name [C] | R/W | Function
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| 31:16 | _CSR_MIP_FIRQ15P_ : _CSR_MIP_FIRQ0P_ | r/- | fast interrupt channel 15..0 pending
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| 31:16 | _CSR_MIP_FIRQ15P_ : _CSR_MIP_FIRQ0P_ | r/w | fast interrupt channel 15..0 pending; cleared request by writing 1
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| 11 | _CSR_MIP_MEIP_ | r/- | machine _external_ interrupt pending
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| 11 | _CSR_MIP_MEIP_ | r/- | machine _external_ interrupt pending; _cleared by user-defined mechanism_
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| 7 | _CSR_MIP_MTIP_ | r/- | machine _timer_ interrupt pending
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| 7 | _CSR_MIP_MTIP_ | r/- | machine _timer_ interrupt pending; cleared by incrementing MTIME's time compare register
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| 3 | _CSR_MIP_MSIP_ | r/- | machine _software_ interrupt pending
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| 3 | _CSR_MIP_MSIP_ | r/- | machine _software_ interrupt pending; _cleared by user-defined mechanism_
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|=======================
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|=======================
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[IMPORTAN]
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The NEORV32 `mip` CSR is read-only. However, a write access will _NOT_ raise an illegal instruction exception.
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// ####################################################################################################################
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// ####################################################################################################################
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:sectnums:
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:sectnums:
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==== Machine Physical Memory Protection CSRs
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==== Machine Physical Memory Protection CSRs
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