| Line 471... |
Line 471... |
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The available physical memory protection logic is configured via the _PMP_NUM_REGIONS_ and
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The available physical memory protection logic is configured via the _PMP_NUM_REGIONS_ and
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_PMP_MIN_GRANULARITY_ top entity generics. _PMP_NUM_REGIONS_ defines the number of implemented
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_PMP_MIN_GRANULARITY_ top entity generics. _PMP_NUM_REGIONS_ defines the number of implemented
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protection regions and thus, the availability of the according `pmpcfg*` and `pmpaddr*` CSRs.
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protection regions and thus, the availability of the according `pmpcfg*` and `pmpaddr*` CSRs.
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[TIP]
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[NOTE]
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If trying to access an PMP-related CSR beyond _PMP_NUM_REGIONS_ **no illegal instruction
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If trying to access an PMP-related CSR beyond _PMP_NUM_REGIONS_ **no illegal instruction
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exception** is triggered. The according CSRs are read-only (writes are ignored) and always return zero.
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exception** is triggered. The according CSRs are read-only (writes are ignored) and always return zero.
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[IMPORTANT]
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[IMPORTANT]
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The RISC-V-compatible NEORV32 physical memory protection only implements the _NAPOT_
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The RISC-V-compatible NEORV32 physical memory protection only implements the **NAPOT**
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(naturally aligned power-of-two region) mode with a minimal region granularity of 8 bytes.
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(naturally aligned power-of-two region) mode yet with a minimal region granularity of 8 bytes.
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:sectnums!:
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:sectnums!:
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===== **`pmpcfg`**
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===== **`pmpcfg`**
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| Line 498... |
Line 498... |
.Physical memory protection configuration register entry
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.Physical memory protection configuration register entry
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[cols="^1,^3,^1,<11"]
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[cols="^1,^3,^1,<11"]
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
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| Bit | RISC-V name | R/W | Function
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| Bit | RISC-V name | R/W | Function
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| 7 | _L_ | r/w | lock bit, can be set - but not be cleared again (only via CPU reset)
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| 7 | _L_ | r/w | lock bit, can only be cleared by CPU reset
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| 6:5 | - | r/- | reserved, read as zero
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| 6:5 | - | r/- | reserved, read as zero
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| 4:3 | _A_ | r/w | mode configuration; only OFF (`00`) and NAPOT (`11`) are supported
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| 4:3 | _A_ | r/w | mode configuration; only OFF (`00`) and NAPOT (`11`) are supported
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| 2 | _X_ | r/w | execute permission
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| 2 | _X_ | r/w | execute permission
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| 1 | _W_ | r/w | write permission
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| 1 | _W_ | r/w | write permission
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| 0 | _R_ | r/w | read permission
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| 0 | _R_ | r/w | read permission
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Line 513... |
===== **`pmpaddr`**
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===== **`pmpaddr`**
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[cols="4,27,>7"]
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[cols="4,27,>7"]
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[frame="topbot",grid="none"]
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[frame="topbot",grid="none"]
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|======
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|======
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| 0x3b0 - 0x3ef| **Physical memory protection configuration registers** | `pmpaddr0` - `pmpaddr63`
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| 0x3b0 - 0x3ef| **Physical memory protection address registers** | `pmpaddr0` - `pmpaddr63`
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3+| Reset value: _UNDEFINED_
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3+| Reset value: _UNDEFINED_
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3+| The `pmpaddr*` CSRs are compatible to the RISC-V specifications. They are used to configure the base
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3+| The `pmpaddr*` CSRs are compatible to the RISC-V specifications. They are used to configure the PMP region's base
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address and the region size.
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address and the region size.
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|======
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|======
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[NOTE]
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[NOTE]
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When configuring PMP make sure to set `pmpaddr*` before activating the according region via
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When configuring PMP make sure to set `pmpaddr*` before activating the according region via
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| Line 609... |
Line 609... |
|======
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|======
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| 0xb00 | **Machine cycle counter - low word** | `mcycle`
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| 0xb00 | **Machine cycle counter - low word** | `mcycle`
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| 0xb80 | **Machine cycle counter - high word** | `mcycleh`
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| 0xb80 | **Machine cycle counter - high word** | `mcycleh`
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3+| Reset value: _UNDEFINED_
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3+| Reset value: _UNDEFINED_
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3+| The `mcycle[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit cycle
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3+| The `mcycle[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit cycle
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counter. The `mcycle[h]` CSR can also be written when in machine mode and is copied to the `cycle[h]` CSR.
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counter. The `mcycle[h]` CSR can also be written when in machine mode and is mirrored to the `cycle[h]` CSR.
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|======
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|======
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:sectnums!:
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:sectnums!:
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===== **`minstret[h]`**
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===== **`minstret[h]`**
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Line 623... |
|======
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|======
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| 0xb02 | **Machine instructions-retired counter - low word** | `minstret`
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| 0xb02 | **Machine instructions-retired counter - low word** | `minstret`
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| 0xb82 | **Machine instructions-retired counter - high word** | `minstreth`
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| 0xb82 | **Machine instructions-retired counter - high word** | `minstreth`
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3+| Reset value: _UNDEFINED_
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3+| Reset value: _UNDEFINED_
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3+| The `minstret[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit retired
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3+| The `minstret[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit retired
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instructions counter. The `minstret[h]` CSR also be written when in machine mode and is copied to the `instret[h]` CSR.
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instructions counter. The `minstret[h]` CSR also be written when in machine mode and is mirrored to the `instret[h]` CSR.
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|======
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|======
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