| Line 28... |
Line 28... |
The description of each single CSR provides the following summary:
|
The description of each single CSR provides the following summary:
|
|
|
.CSR description
|
.CSR description
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| _Address_ | _Description_ | _ASM alias_
|
| _Address_ | _Description_ | _ASM alias_
|
3+| Reset value: _CSR content after hardware reset_ (also see <<_cpu_hardware_reset>>)
|
3+| Reset value: _CSR content after hardware reset_ (also see <<_cpu_hardware_reset>>)
|
3+| _Detailed description_
|
3+| _Detailed description_
|
|======
|
|=======================
|
|
|
.Not Implemented CSRs / CSR Bits
|
.Not Implemented CSRs / CSR Bits
|
[IMPORTANT]
|
[IMPORTANT]
|
All CSR bits that are unused / not implemented / not shown are _hardwired to zero_. All CSRs that are not
|
All CSR bits that are unused / not implemented / not shown are _hardwired to zero_. All CSRs that are not
|
implemented at all (and are not "disabled" using certain configuration generics) will trigger an exception on
|
implemented at all (and are not "disabled" using certain configuration generics) will trigger an exception on
|
| Line 108... |
Line 108... |
| 0xf11 | <<_mvendorid>> | _CSR_MVENDORID_ | r/- | Vendor ID |
|
| 0xf11 | <<_mvendorid>> | _CSR_MVENDORID_ | r/- | Vendor ID |
|
| 0xf12 | <<_marchid>> | _CSR_MARCHID_ | r/- | Architecture ID |
|
| 0xf12 | <<_marchid>> | _CSR_MARCHID_ | r/- | Architecture ID |
|
| 0xf13 | <<_mimpid>> | _CSR_MIMPID_ | r/- | Machine implementation ID / version |
|
| 0xf13 | <<_mimpid>> | _CSR_MIMPID_ | r/- | Machine implementation ID / version |
|
| 0xf14 | <<_mhartid>> | _CSR_MHARTID_ | r/- | Machine thread ID |
|
| 0xf14 | <<_mhartid>> | _CSR_MHARTID_ | r/- | Machine thread ID |
|
| 0xf15 | <<_mconfigptr>> | _CSR_MCONFIGPTR_ | r/- | Machine configuration pointer register |
|
| 0xf15 | <<_mconfigptr>> | _CSR_MCONFIGPTR_ | r/- | Machine configuration pointer register |
|
|
6+^| **<<_neorv32_specific_csrs>>**
|
|
| 0xfc0 | <<_mxisa>> | _CSR_MXISA_ | r/- | NEORV32-specific "extended" machine CPU ISA and extensions |
|
|=======================
|
|=======================
|
|
|
|
|
|
|
|
|
| Line 126... |
Line 128... |
:sectnums!:
|
:sectnums!:
|
===== **`fflags`**
|
===== **`fflags`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x001 | **Floating-point accrued exceptions** | `fflags`
|
| 0x001 | **Floating-point accrued exceptions** | `fflags`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `fflags` CSR is compatible to the RISC-V specifications. It shows the accrued ("accumulated")
|
3+| The `fflags` CSR is compatible to the RISC-V specifications. It shows the accrued ("accumulated")
|
exception flags in the lowest 5 bits. This CSR is only available if a floating-point CPU extension is enabled.
|
exception flags in the lowest 5 bits. This CSR is only available if a floating-point CPU extension is enabled.
|
See the RISC-V ISA spec for more information.
|
See the RISC-V ISA spec for more information.
|
|======
|
|=======================
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`frm`**
|
===== **`frm`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x002 | **Floating-point dynamic rounding mode** | `frm`
|
| 0x002 | **Floating-point dynamic rounding mode** | `frm`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `frm` CSR is compatible to the RISC-V specifications and is used to configure the rounding modes using
|
3+| The `frm` CSR is compatible to the RISC-V specifications and is used to configure the rounding modes using
|
the lowest 3 bits. This CSR is only available if a floating-point CPU extension is enabled. See the RISC-V
|
the lowest 3 bits. This CSR is only available if a floating-point CPU extension is enabled. See the RISC-V
|
ISA spec for more information.
|
ISA spec for more information.
|
|======
|
|=======================
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`fcsr`**
|
===== **`fcsr`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x003 | **Floating-point control and status register** | `fcsr`
|
| 0x003 | **Floating-point control and status register** | `fcsr`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `fcsr` CSR is compatible to the RISC-V specifications. It provides combined read/write access to the
|
3+| The `fcsr` CSR is compatible to the RISC-V specifications. It provides combined read/write access to the
|
`fflags` and `frm` CSRs. This CSR is only available if a floating-point CPU extension is enabled. See the
|
`fflags` and `frm` CSRs. This CSR is only available if a floating-point CPU extension is enabled. See the
|
RISC-V ISA spec for more information.
|
RISC-V ISA spec for more information.
|
|======
|
|=======================
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
| Line 173... |
Line 175... |
:sectnums!:
|
:sectnums!:
|
===== **`menvcfg`**
|
===== **`menvcfg`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x30a | **Machine environment configuration register** | `menvcfg`
|
| 0x30a | **Machine environment configuration register** | `menvcfg`
|
3+| Reset value: _0x00000000_
|
3+| Reset value: _0x00000000_
|
3+| The features of this CSR are not implemented yet. The register is read-only. NOTE: This register
|
3+| The features of this CSR are not implemented yet. The register is read-only. NOTE: This register
|
only exists if the `U` ISA extensions is enabled.
|
only exists if the `U` ISA extensions is enabled.
|
|======
|
|=======================
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`menvcfgh`**
|
===== **`menvcfgh`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x31a | **Machine environment configuration register - high word** | `menvcfgh`
|
| 0x31a | **Machine environment configuration register - high word** | `menvcfgh`
|
3+| Reset value: _0x00000000_
|
3+| Reset value: _0x00000000_
|
3+| The features of this CSR are not implemented yet. The register is read-only. NOTE: This register
|
3+| The features of this CSR are not implemented yet. The register is read-only. NOTE: This register
|
only exists if the `U` ISA extensions is enabled.
|
only exists if the `U` ISA extensions is enabled.
|
|======
|
|=======================
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
| Line 204... |
Line 206... |
:sectnums!:
|
:sectnums!:
|
===== **`mstatus`**
|
===== **`mstatus`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x300 | **Machine status register** | `mstatus`
|
| 0x300 | **Machine status register** | `mstatus`
|
3+| Reset value: _0x00000000_
|
3+| Reset value: _0x00000000_
|
3+| The `mstatus` CSR is compatible to the RISC-V specifications. It shows the CPU's current execution state.
|
3+| The `mstatus` CSR is compatible to the RISC-V specifications. It shows the CPU's current execution state.
|
The following bits are implemented (all remaining bits are always zero and are read-only).
|
The following bits are implemented (all remaining bits are always zero and are read-only).
|
|======
|
|=======================
|
|
|
.Machine status register
|
.Machine status register
|
[cols="^1,<3,^1,<5"]
|
[cols="^1,<3,^1,<5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Line 230... |
Line 232... |
:sectnums!:
|
:sectnums!:
|
===== **`misa`**
|
===== **`misa`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x301 | **ISA and extensions** | `misa`
|
| 0x301 | **ISA and extensions** | `misa`
|
3+| Reset value: _configuration dependant_
|
3+| Reset value: _defined_
|
3+| The `misa` CSR gives information about the actual CPU features. The lowest 26 bits show the implemented
|
3+| The `misa` CSR gives information about the actual CPU features. The lowest 26 bits show the implemented
|
CPU extensions. The following bits are implemented (all remaining bits are always zero and are read-only).
|
CPU extensions. The following bits are implemented (all remaining bits are always zero and are read-only).
|
|======
|
|=======================
|
|
|
[IMPORTANT]
|
[IMPORTANT]
|
The `misa` CSR is not fully RISC-V-compatible as it is read-only. Hence, implemented CPU
|
The `misa` CSR is not fully RISC-V-compatible as it is read-only. Hence, implemented CPU
|
extensions cannot be switch on/off during runtime. For compatibility reasons any write access to this
|
extensions cannot be switch on/off during runtime. For compatibility reasons any write access to this
|
CSR is simply ignored and will _NOT_ cause an illegal instruction exception.
|
CSR is simply ignored and will _NOT_ cause an illegal instruction exception.
|
| Line 258... |
Line 260... |
| 2 | _CSR_MISA_C_EXT_ | r/- | `C` CPU extension (compressed instruction) available, set when _CPU_EXTENSION_RISCV_C_ enabled
|
| 2 | _CSR_MISA_C_EXT_ | r/- | `C` CPU extension (compressed instruction) available, set when _CPU_EXTENSION_RISCV_C_ enabled
|
| 0 | _CSR_MISA_A_EXT_ | r/- | `A` CPU extension (atomic memory access) available, set when _CPU_EXTENSION_RISCV_A_ enabled
|
| 0 | _CSR_MISA_A_EXT_ | r/- | `A` CPU extension (atomic memory access) available, set when _CPU_EXTENSION_RISCV_A_ enabled
|
|=======================
|
|=======================
|
|
|
[TIP]
|
[TIP]
|
Information regarding the implemented RISC-V `Z*` _sub-extensions_ (like `Zicsr` or `Zfinx`) can be found
|
Machine-mode software can discover available `Z*` _sub-extensions_ (like `Zicsr` or `Zfinx`) by checking the NEORV32-specific
|
in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
|
<<_mxisa>> CSR.
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`mie`**
|
===== **`mie`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x304 | **Machine interrupt-enable register** | `mie`
|
| 0x304 | **Machine interrupt-enable register** | `mie`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `mie` CSR is compatible to the RISC-V specifications and features custom extensions for the fast
|
3+| The `mie` CSR is compatible to the RISC-V specifications and features custom extensions for the fast
|
interrupt channels. It is used to enabled specific interrupts sources. Please note that interrupts also have to be
|
interrupt channels. It is used to enabled specific interrupts sources. Please note that interrupts also have to be
|
globally enabled via the `CSR_MSTATUS_MIE` flag of the `mstatus` CSR. The following bits are implemented
|
globally enabled via the `CSR_MSTATUS_MIE` flag of the `mstatus` CSR. The following bits are implemented
|
(all remaining bits are always zero and are read-only):
|
(all remaining bits are always zero and are read-only):
|
|======
|
|=======================
|
|
|
.Machine ISA and extension register
|
.Machine ISA and extension register
|
[cols="^1,<3,^1,<5"]
|
[cols="^1,<3,^1,<5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Line 293... |
Line 295... |
:sectnums!:
|
:sectnums!:
|
===== **`mtvec`**
|
===== **`mtvec`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x305 | **Machine trap-handler base address** | `mtvec`
|
| 0x305 | **Machine trap-handler base address** | `mtvec`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `mtvec` CSR is compatible to the RISC-V specifications. It stores the base address for ALL machine
|
3+| The `mtvec` CSR is compatible to the RISC-V specifications. It stores the base address for ALL machine
|
traps. Thus, it defines the main entry point for exception/interrupt handling regardless of the actual trap
|
traps. Thus, it defines the main entry point for exception/interrupt handling regardless of the actual trap
|
source. The lowest two bits of this register are always zero and cannot be modified (= address mode only).
|
source. The lowest two bits of this register are always zero and cannot be modified (= address mode only).
|
|======
|
|=======================
|
|
|
.Machine trap-handler base address
|
.Machine trap-handler base address
|
[cols="^1,^1,<8"]
|
[cols="^1,^1,<8"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Line 316... |
Line 318... |
:sectnums!:
|
:sectnums!:
|
===== **`mcounteren`**
|
===== **`mcounteren`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x306 | **Machine counter enable** | `mcounteren`
|
| 0x306 | **Machine counter enable** | `mcounteren`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `mcounteren` CSR is compatible to the RISC-V specifications. The bits of this CSR define which
|
3+| The `mcounteren` CSR is compatible to the RISC-V specifications. The bits of this CSR define which
|
counter/timer CSR can be accessed (read) from code running in a less-privileged modes. For example,
|
counter/timer CSR can be accessed (read) from code running in a less-privileged modes. For example,
|
if user-level code tries to read from a counter/timer CSR without enabled access, an illegal instruction
|
if user-level code tries to read from a counter/timer CSR without enabled access, an illegal instruction
|
exception is raised. NOTE: If the `U` ISA extension is not enabled this CSR does not exist.
|
exception is raised. NOTE: If the `U` ISA extension is not enabled this CSR does not exist.
|
|======
|
|=======================
|
|
|
.Machine counter enable register
|
.Machine counter enable register
|
[cols="^1,<3,^1,<5"]
|
[cols="^1,<3,^1,<5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Line 342... |
Line 344... |
:sectnums!:
|
:sectnums!:
|
===== **`mstatush`**
|
===== **`mstatush`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x310 | **Machine status register - high word** | `mstatush`
|
| 0x310 | **Machine status register - high word** | `mstatush`
|
3+| Reset value: _0x00000000_
|
3+| Reset value: _0x00000000_
|
3+| The `mstatush` CSR is compatible to the RISC-V specifications. In combination with <<_mstatus>> it shows additional
|
3+| The `mstatush` CSR is compatible to the RISC-V specifications. In combination with <<_mstatus>> it shows additional
|
execution state information. The NEORV32 `mstatush` CSR is read-only and all bits are hardwired to zero.
|
execution state information. The NEORV32 `mstatush` CSR is read-only and all bits are hardwired to zero.
|
|======
|
|=======================
|
|
|
[NOTE]
|
[NOTE]
|
The NEORV32 `mstatush` CSR is not a physical register. All write access are ignored and all read accesses will always
|
The NEORV32 `mstatush` CSR is not a physical register. All write access are ignored and all read accesses will always
|
return zero. However, any access will not raise an illegal instruction exception. The CSR address is implemented
|
return zero. However, any access will not raise an illegal instruction exception. The CSR address is implemented
|
in order to comply with the RISC-V privilege architecture specs.
|
in order to comply with the RISC-V privilege architecture specs.
|
| Line 366... |
Line 368... |
:sectnums!:
|
:sectnums!:
|
===== **`mscratch`**
|
===== **`mscratch`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x340 | **Scratch register for machine trap handlers** | `mscratch`
|
| 0x340 | **Scratch register for machine trap handlers** | `mscratch`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `mscratch` CSR is compatible to the RISC-V specifications. It is a general purpose scratch register that
|
3+| The `mscratch` CSR is compatible to the RISC-V specifications. It is a general purpose scratch register that
|
can be used by the exception/interrupt handler. The content pf this register after reset is undefined.
|
can be used by the exception/interrupt handler. The content pf this register after reset is undefined.
|
|======
|
|=======================
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`mepc`**
|
===== **`mepc`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x341 | **Machine exception program counter** | `mepc`
|
| 0x341 | **Machine exception program counter** | `mepc`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `mepc` CSR is compatible to the RISC-V specifications. For exceptions (like an illegal instruction) this
|
3+| The `mepc` CSR is compatible to the RISC-V specifications. For exceptions (like an illegal instruction) this
|
register provides the address of the exception-causing instruction. For Interrupt (like a machine timer
|
register provides the address of the exception-causing instruction. For Interrupt (like a machine timer
|
interrupt) this register provides the address of the next not-yet-executed instruction.
|
interrupt) this register provides the address of the next not-yet-executed instruction.
|
|======
|
|=======================
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`mcause`**
|
===== **`mcause`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x342 | **Machine trap cause** | `mcause`
|
| 0x342 | **Machine trap cause** | `mcause`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `mcause` CSR is compatible to the RISC-V specifications. It show the cause ID for a taken exception.
|
3+| The `mcause` CSR is compatible to the RISC-V specifications. It show the cause ID for a taken exception.
|
|======
|
|=======================
|
|
|
.Machine trap cause register
|
.Machine trap cause register
|
[cols="^1,^1,<8"]
|
[cols="^1,^1,<8"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Line 412... |
Line 414... |
:sectnums!:
|
:sectnums!:
|
===== **`mtval`**
|
===== **`mtval`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x343 | **Machine bad address or instruction** | `mtval`
|
| 0x343 | **Machine bad address or instruction** | `mtval`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `mtval` CSR is compatible to the RISC-V specifications. When a trap is triggered, the CSR shows either
|
3+| The `mtval` CSR is compatible to the RISC-V specifications. When a trap is triggered, the CSR shows either
|
the faulting address (for misaligned/faulting load/stores/fetch) or the faulting instruction itself (for illegal
|
the faulting address (for misaligned/faulting load/stores/fetch) or the faulting instruction itself (for illegal
|
instructions). For interrupts the CSR is set to zero.
|
instructions). For interrupts the CSR is set to zero.
|
|======
|
|=======================
|
|
|
.Machine bad address or instruction register
|
.Machine bad address or instruction register
|
[cols="^5,^5"]
|
[cols="^5,^5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Line 440... |
Line 442... |
:sectnums!:
|
:sectnums!:
|
===== **`mip`**
|
===== **`mip`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x344 | **Machine interrupt Pending** | `mip`
|
| 0x344 | **Machine interrupt Pending** | `mip`
|
3+| Reset value: _0x00000000_
|
3+| Reset value: _0x00000000_
|
3+| The `mip` CSR is compatible to the RISC-V specifications and also provides custom extensions. It shows currently _pending_ interrupts.
|
3+| The `mip` CSR is compatible to the RISC-V specifications and also provides custom extensions. It shows currently _pending_ interrupts.
|
The bits for the standard RISC-V interrupts are read-only. Hence, these interrupts cannot be cleared using the `mip` register and must
|
The bits for the standard RISC-V interrupts are read-only. Hence, these interrupts cannot be cleared using the `mip` register and must
|
be cleared/acknowledged within the according interrupt-generating device.
|
be cleared/acknowledged within the according interrupt-generating device.
|
The upper 16 bits represent the status of the CPU's fast interrupt request lines (FIRQ). Once triggered, these _have to be cleared_ again by setting
|
The upper 16 bits represent the status of the CPU's fast interrupt request lines (FIRQ). Once triggered, these _have to be cleared_ again by setting
|
the according `mip` bit in the interrupt handler routine to clear the current interrupt request.
|
the according `mip` bit in the interrupt handler routine to clear the current interrupt request.
|
|======
|
|=======================
|
|
|
.Machine interrupt pending register
|
.Machine interrupt pending register
|
[cols="^1,<3,^1,<5"]
|
[cols="^1,<3,^1,<5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Line 485... |
Line 487... |
:sectnums!:
|
:sectnums!:
|
===== **`pmpcfg`**
|
===== **`pmpcfg`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x3a0 - 0x3af| **Physical memory protection configuration registers** | `pmpcfg0` - `pmpcfg15`
|
| 0x3a0 - 0x3af| **Physical memory protection configuration registers** | `pmpcfg0` - `pmpcfg15`
|
3+| Reset value: _0x00000000_
|
3+| Reset value: _0x00000000_
|
3+| The `pmpcfg*` CSRs are compatible to the RISC-V specifications. They are used to configure the protected
|
3+| The `pmpcfg*` CSRs are compatible to the RISC-V specifications. They are used to configure the protected
|
regions, where each `pmpcfg*` CSR provides configuration bits for four regions. The following bits (for the
|
regions, where each `pmpcfg*` CSR provides configuration bits for four regions. The following bits (for the
|
first PMP configuration entry) are implemented (all remaining bits are always zero and are read-only):
|
first PMP configuration entry) are implemented (all remaining bits are always zero and are read-only):
|
|======
|
|=======================
|
|
|
.Physical memory protection configuration register entry
|
.Physical memory protection configuration register entry
|
[cols="^1,^3,^1,<11"]
|
[cols="^1,^3,^1,<11"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Line 512... |
Line 514... |
:sectnums!:
|
:sectnums!:
|
===== **`pmpaddr`**
|
===== **`pmpaddr`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x3b0 - 0x3ef| **Physical memory protection address registers** | `pmpaddr0` - `pmpaddr63`
|
| 0x3b0 - 0x3ef| **Physical memory protection address registers** | `pmpaddr0` - `pmpaddr63`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `pmpaddr*` CSRs are compatible to the RISC-V specifications. They are used to configure the PMP region's base
|
3+| The `pmpaddr*` CSRs are compatible to the RISC-V specifications. They are used to configure the PMP region's base
|
address and the region size.
|
address and the region size.
|
|======
|
|=======================
|
|
|
[NOTE]
|
[NOTE]
|
When configuring PMP make sure to set `pmpaddr*` before activating the according region via
|
When configuring PMP make sure to set `pmpaddr*` before activating the according region via
|
`pmpcfg*`. When changing the PMP configuration, deactivate the according region via `pmpcfg*`
|
`pmpcfg*`. When changing the PMP configuration, deactivate the according region via `pmpcfg*`
|
before modifying `pmpaddr*`.
|
before modifying `pmpaddr*`.
|
| Line 543... |
Line 545... |
|
|
.Effective CPU counter width (`[m]cycle` & `[m]instret`)
|
.Effective CPU counter width (`[m]cycle` & `[m]instret`)
|
[IMPORTANT]
|
[IMPORTANT]
|
If _CPU_CNT_WIDTH_ is less than 64 (the default value) and greater than or equal 32, the according
|
If _CPU_CNT_WIDTH_ is less than 64 (the default value) and greater than or equal 32, the according
|
MSBs of `[m]cycleh` and `[m]instreth` are read-only and always read as zero. This configuration
|
MSBs of `[m]cycleh` and `[m]instreth` are read-only and always read as zero. This configuration
|
will also set the _SYSINFO_CPU_ZXSCNT_ flag ("small counters") in the `CPU`
|
will also set the _CSR_MXISA_ZXSCNT_ flag ("small counters") in the <<_mxisa>> CSR. +
|
<<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +
|
|
+
|
+
|
If _CPU_CNT_WIDTH_ is less than 32 and greater than 0, the `[m]cycleh` and `[m]instreth` CSRs are hardwired to zero
|
If _CPU_CNT_WIDTH_ is less than 32 and greater than 0, the `[m]cycleh` and `[m]instreth` CSRs are hardwired to zero
|
and any write access to them is ignored. Furthermore, the according MSBs of `[m]cycle` and `[m]instret` are read-only
|
and any write access to them is ignored. Furthermore, the according MSBs of `[m]cycle` and `[m]instret` are read-only
|
and always read as zero. This configuration will also set the _SYSINFO_CPU_ZXSCNT_ flag ("small counters") in
|
and always read as zero. This configuration will also set the _CSR_MXISA_ZXSCNT_ flag ("small counters") in
|
the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +
|
the <<_mxisa>> CSR. +
|
+
|
+
|
If _CPU_CNT_WIDTH_ is 0, the <<_cycleh>> and <<_instreth>> / <<_mcycleh>> and <<_minstreth>> CSRs are hardwired to zero
|
If _CPU_CNT_WIDTH_ is 0, the <<_cycleh>> and <<_instreth>> / <<_mcycleh>> and <<_minstreth>> CSRs are hardwired to zero
|
and any write access to them is ignored.
|
and any write access to them is ignored.
|
|
|
|
.Counter Increment During Debugging
|
|
[NOTE]
|
|
The `[m]cycle[h]` and `[m]instret[h]` counters do not increment when the CPU is in debug mode.
|
|
See section <<_cpu_debug_mode>> for more information.
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`cycle[h]`**
|
===== **`cycle[h]`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0xc00 | **Cycle counter - low word** | `cycle`
|
| 0xc00 | **Cycle counter - low word** | `cycle`
|
| 0xc80 | **Cycle counter - high word** | `cycleh`
|
| 0xc80 | **Cycle counter - high word** | `cycleh`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `cycle[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit cycle
|
3+| The `cycle[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit cycle
|
counter. The `cycle[h]` CSR is a read-only shadowed copy of the `mcycle[h]` CSR.
|
counter. The `cycle[h]` CSR is a read-only shadowed copy of the `mcycle[h]` CSR.
|
|======
|
|=======================
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`time[h]`**
|
===== **`time[h]`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0xc01 | **System time - low word** | `time`
|
| 0xc01 | **System time - low word** | `time`
|
| 0xc81 | **System time - high word** | `timeh`
|
| 0xc81 | **System time - high word** | `timeh`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `time[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit system
|
3+| The `time[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit system
|
time. The system time is either generated by the processor-internal _MTIME_ system timer unit (if _IO_MTIME_EN_ = _true_) or can be provided by an
|
time. The system time is either generated by the processor-internal _MTIME_ system timer unit (if _IO_MTIME_EN_ = _true_) or can be provided by an
|
external timer unit via the processor's `mtime_i` signal (if _IO_MTIME_EN_ = _false_).
|
external timer unit via the processor's `mtime_i` signal (if _IO_MTIME_EN_ = _false_).
|
CSR is read-only. Change the system time via the _MTIME_ unit.
|
CSR is read-only. Change the system time via the _MTIME_ unit.
|
|======
|
|=======================
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`instret[h]`**
|
===== **`instret[h]`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0xc02 | **Instructions-retired counter - low word** | `instret`
|
| 0xc02 | **Instructions-retired counter - low word** | `instret`
|
| 0xc82 | **Instructions-retired counter - high word** | `instreth`
|
| 0xc82 | **Instructions-retired counter - high word** | `instreth`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `instret[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit retired
|
3+| The `instret[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit retired
|
instructions counter. The `instret[h]` CSR is a read-only shadowed copy of the `minstret[h]` CSR.
|
instructions counter. The `instret[h]` CSR is a read-only shadowed copy of the `minstret[h]` CSR.
|
|======
|
|=======================
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`mcycle[h]`**
|
===== **`mcycle[h]`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0xb00 | **Machine cycle counter - low word** | `mcycle`
|
| 0xb00 | **Machine cycle counter - low word** | `mcycle`
|
| 0xb80 | **Machine cycle counter - high word** | `mcycleh`
|
| 0xb80 | **Machine cycle counter - high word** | `mcycleh`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `mcycle[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit cycle
|
3+| The `mcycle[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit cycle
|
counter. The `mcycle[h]` CSR can also be written when in machine mode and is mirrored to the `cycle[h]` CSR.
|
counter. The `mcycle[h]` CSR can also be written when in machine mode and is mirrored to the `cycle[h]` CSR.
|
|======
|
|=======================
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`minstret[h]`**
|
===== **`minstret[h]`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0xb02 | **Machine instructions-retired counter - low word** | `minstret`
|
| 0xb02 | **Machine instructions-retired counter - low word** | `minstret`
|
| 0xb82 | **Machine instructions-retired counter - high word** | `minstreth`
|
| 0xb82 | **Machine instructions-retired counter - high word** | `minstreth`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `minstret[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit retired
|
3+| The `minstret[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit retired
|
instructions counter. The `minstret[h]` CSR also be written when in machine mode and is mirrored to the `instret[h]` CSR.
|
instructions counter. The `minstret[h]` CSR also be written when in machine mode and is mirrored to the `instret[h]` CSR.
|
|======
|
|=======================
|
|
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
| Line 658... |
Line 664... |
The total LSB-aligned HPM counter size (low word CSR + high word CSR) is defined via the
|
The total LSB-aligned HPM counter size (low word CSR + high word CSR) is defined via the
|
<<_hpm_num_cnts>> generic (0..64-bit). If <<_hpm_num_cnts>> is less than 64, all unused MSB-aligned
|
<<_hpm_num_cnts>> generic (0..64-bit). If <<_hpm_num_cnts>> is less than 64, all unused MSB-aligned
|
bits are hardwired to zero.
|
bits are hardwired to zero.
|
|
|
|
|
|
.Counter Increment During Debugging
|
|
[NOTE]
|
|
All HPM counters do not increment when the CPU is in debug mode.
|
|
See section <<_cpu_debug_mode>> for more information.
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`mhpmevent`**
|
===== **`mhpmevent`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x232 -0x33f | **Machine hardware performance monitor event selector** | `mhpmevent3` - `mhpmevent31`
|
| 0x232 -0x33f | **Machine hardware performance monitor event selector** | `mhpmevent3` - `mhpmevent31`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `mhpmevent*` CSRs are compatible to the RISC-V specifications. The configuration of these CSR define
|
3+| The `mhpmevent*` CSRs are compatible to the RISC-V specifications. The configuration of these CSR define
|
the architectural events that cause the according `mhpmcounter*[h]` counters to increment. All available events are
|
the architectural events that cause the according `mhpmcounter*[h]` counters to increment. All available events are
|
listed in the table below. If more than one event is selected, the according counter will increment if any of
|
listed in the table below. If more than one event is selected, the according counter will increment if any of
|
the enabled events is observed (logical OR). Note that the counter will only increment by 1 step per clock
|
the enabled events is observed (logical OR). Note that the counter will only increment by 1 step per clock
|
cycle even if more than one event is observed. If the CPU is in sleep mode, no HPM counter will increment
|
cycle even if more than one event is observed. If the CPU is in sleep mode, no HPM counter will increment
|
at all.
|
at all.
|
|======
|
|=======================
|
|
|
The available hardware performance logic is configured via the _HPM_NUM_CNTS_ top entity generic.
|
The available hardware performance logic is configured via the _HPM_NUM_CNTS_ top entity generic.
|
_HPM_NUM_CNTS_ defines the number of implemented performance monitors and thus, the availability of the
|
_HPM_NUM_CNTS_ defines the number of implemented performance monitors and thus, the availability of the
|
according `mhpmcounter*[h]` and `mhpmevent*` CSRs.
|
according `mhpmcounter*[h]` and `mhpmevent*` CSRs.
|
|
|
| Line 706... |
Line 718... |
:sectnums!:
|
:sectnums!:
|
===== **`mhpmcounter[h]`**
|
===== **`mhpmcounter[h]`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0xb03 - 0xb1f | **Machine hardware performance monitor - counter low** | `mhpmcounter3` - `mhpmcounter31`
|
| 0xb03 - 0xb1f | **Machine hardware performance monitor - counter low** | `mhpmcounter3` - `mhpmcounter31`
|
| 0xb83 - 0xb9f | **Machine hardware performance monitor - counter high** | `mhpmcounter3h` - `mhpmcounter31h`
|
| 0xb83 - 0xb9f | **Machine hardware performance monitor - counter high** | `mhpmcounter3h` - `mhpmcounter31h`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `mhpmcounter*[h]` CSRs are compatible to the RISC-V specifications. These CSRs provide the lower/upper 32-
|
3+| The `mhpmcounter*[h]` CSRs are compatible to the RISC-V specifications. These CSRs provide the lower/upper 32-
|
bit of arbitrary event counters. The event(s) that trigger an increment of theses counters are selected via the according
|
bit of arbitrary event counters. The event(s) that trigger an increment of theses counters are selected via the according
|
`mhpmevent*` CSRs bits.
|
`mhpmevent*` CSRs bits.
|
|======
|
|=======================
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
| Line 726... |
Line 738... |
:sectnums!:
|
:sectnums!:
|
===== **`mcountinhibit`**
|
===== **`mcountinhibit`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0x320 | **Machine counter-inhibit register** | `mcountinhibit`
|
| 0x320 | **Machine counter-inhibit register** | `mcountinhibit`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `mcountinhibit` CSR is compatible to the RISC-V specifications. The bits in this register define which
|
3+| The `mcountinhibit` CSR is compatible to the RISC-V specifications. The bits in this register define which
|
counter/timer CSR are allowed to perform an automatic increment. Automatic update is enabled if the
|
counter/timer CSR are allowed to perform an automatic increment. Automatic update is enabled if the
|
according bit in `mcountinhibit` is cleared. The following bits are implemented (all remaining bits are
|
according bit in `mcountinhibit` is cleared. The following bits are implemented (all remaining bits are
|
always zero and are read-only).
|
always zero and are read-only).
|
|======
|
|=======================
|
|
|
.Machine counter-inhibit register
|
.Machine counter-inhibit register
|
[cols="^1,<3,^1,<5"]
|
[cols="^1,<3,^1,<5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Line 759... |
Line 771... |
:sectnums!:
|
:sectnums!:
|
===== **`mvendorid`**
|
===== **`mvendorid`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0xf11 | **Machine vendor ID** | `mvendorid`
|
| 0xf11 | **Machine vendor ID** | `mvendorid`
|
3+| Reset value: _0x00000000_
|
3+| Reset value: _0x00000000_
|
3+| The `mvendorid` CSR is compatible to the RISC-V specifications. It is read-only and always reads zero.
|
3+| The `mvendorid` CSR is compatible to the RISC-V specifications. It is read-only and always reads zero.
|
|======
|
|=======================
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`marchid`**
|
===== **`marchid`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0xf12 | **Machine architecture ID** | `marchid`
|
| 0xf12 | **Machine architecture ID** | `marchid`
|
3+| Reset value: _0x00000013_
|
3+| Reset value: _0x00000013_
|
3+| The `marchid` CSR is compatible to the RISC-V specifications. It is read-only and shows the NEORV32
|
3+| The `marchid` CSR is compatible to the RISC-V specifications. It is read-only and shows the NEORV32
|
official _RISC-V open-source architecture ID_ (decimal: 19, 32-bit hexadecimal: 0x00000013).
|
official _RISC-V open-source architecture ID_ (decimal: 19, 32-bit hexadecimal: 0x00000013).
|
|======
|
|=======================
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`mimpid`**
|
===== **`mimpid`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0xf13 | **Machine implementation ID** | `mimpid`
|
| 0xf13 | **Machine implementation ID** | `mimpid`
|
3+| Reset value: _HW version number_
|
3+| Reset value: _defined_
|
3+| The `mimpid` CSR is compatible to the RISC-V specifications. It is read-only and shows the version of the
|
3+| The `mimpid` CSR is compatible to the RISC-V specifications. It is read-only and shows the version of the
|
NEORV32 as BCD-coded number (example: `mimpid` = _0x01020312_ → 01.02.03.12 → version 1.2.3.12).
|
NEORV32 as BCD-coded number (example: `mimpid` = _0x01020312_ → 01.02.03.12 → version 1.2.3.12).
|
|======
|
|=======================
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`mhartid`**
|
===== **`mhartid`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0xf14 | **Machine hardware thread ID** | `mhartid`
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| 0xf14 | **Machine hardware thread ID** | `mhartid`
|
3+| Reset value: _HW_THREAD_ID_ generic
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3+| Reset value: _defined_
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3+| The `mhartid` CSR is compatible to the RISC-V specifications. It is read-only and shows the core's hart ID,
|
3+| The `mhartid` CSR is compatible to the RISC-V specifications. It is read-only and shows the core's hart ID,
|
which is assigned via the CPU's _HW_THREAD_ID_ generic.
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which is assigned via the CPU's _HW_THREAD_ID_ generic.
|
|======
|
|=======================
|
|
|
|
|
:sectnums!:
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:sectnums!:
|
===== **`mconfigptr`**
|
===== **`mconfigptr`**
|
|
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[cols="4,27,>7"]
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[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|======
|
|=======================
|
| 0xf15 | **Machine configuration pointer register** | `mconfigptr`
|
| 0xf15 | **Machine configuration pointer register** | `mconfigptr`
|
3+| Reset value: `0x00000000`
|
3+| Reset value: _0x00000000_
|
3+| This register holds a physical address (if not zero) that points to the base address of an architecture configuration structure.
|
3+| This register holds a physical address (if not zero) that points to the base address of an architecture configuration structure.
|
Software can traverse this data structure to discover information about the harts, the platform, and their configuration.
|
Software can traverse this data structure to discover information about the harts, the platform, and their configuration.
|
**NOTE: Not assigned yet.**
|
**NOTE: Not assigned yet.**
|
|======
|
|=======================
|
|
|
|
|
|
|
|
// ####################################################################################################################
|
|
:sectnums:
|
|
==== NEORV32-Specific CSRs
|
|
|
|
[NOTE]
|
|
All NEORV32-specific CSRs are mapped to addresses that are explicitly reserved for custom **Machine-Mode, read-only** CSRs
|
|
(assured by the RISC-V privileged specifications). Hence, these CSRs can only be accessed when in machine-mode. Any access
|
|
outside of machine-mode will raise an illegal instruction exception.
|
|
|
|
:sectnums!:
|
|
===== **`mxisa`**
|
|
|
|
[cols="4,27,>7"]
|
|
[frame="topbot",grid="none"]
|
|
|=======================
|
|
| 0x7c0 | **Machine EXTENDED ISA and Extensions register** | `mxisa`
|
|
3+| Reset value: _defined_
|
|
3+| NEORV32-specific read-only CSR that helps machine-mode software to discover `Z*` sub-extensions and CPU options.
|
|
|=======================
|
|
|
|
|
|
.Machine _EXTENDED_ ISA and Extensions register bits
|
|
[cols="^1,<3,^1,<5"]
|
|
[options="header",grid="rows"]
|
|
|=======================
|
|
| Bit | Name [C] | R/W | Function
|
|
| 31 | _CSR_MXISA_FASTSHIFT_ | r/- | fast shifts available when set (via top's <<_fast_shift_en>> generic)
|
|
| 30 | _CSR_MXISA_FASTMUL_ | r/- | fast multiplication available when set (via top's <<_fast_mul_en>> generic)
|
|
| 31:11 | - | r/- | _reserved_, read as zero
|
|
| 10 | _CSR_MXISA_DEBUGMODE_ | r/- | RISC-V CPU `debug_mode` available when set (via top's <<_on_chip_debugger_en>> generic)
|
|
| 9 | _CSR_MXISA_ZIHPM_ | r/- | `Zihpm` (hardware performance monitors) extension available when set (via top's <<_cpu_extension_riscv_zihpm>> generic)
|
|
| 8 | _CSR_MXISA_PMP_ | r/- | PMP` (physical memory protection) extension available when set (via top's <<_pmp_num_regions>> generic)
|
|
| 7 | _CSR_MXISA_ZICNTR_ | r/- | `Zicntr` extension (`I` sub-extension) available when set - `[m]cycle`, `[m]instret` and `[m]time` CSRs available when set (via top's <<_cpu_extension_riscv_zicntr>> generic)
|
|
| 6 | _CSR_MXISA_ZXSCNT_ | r/- | Custom extension - _Small_ CPU counters: `[m]cycle` & `[m]instret` CSRs have less than 64-bit when set (via top's <<_cpu_cnt_width>> generic)
|
|
| 5 | _CSR_MXISA_ZFINX_ | r/- | `Zfinx` extension (`F` sub-/alternative-extension: FPU using `x` registers) available when set (via top's <<_cpu_extension_riscv_zfinx>> generic)
|
|
| 4 | - | r/- | _reserved_, read as zero
|
|
| 3 | _CSR_MXISA_ZXCFU_ | r/- | `Zxcfu` extension (custom functions unit for custom RISC-V instructions) available when set (via top's <<_cpu_extension_riscv_zxcfu>> generic)
|
|
| 2 | _CSR_MXISA_ZMMUL_ | r/- | `Zmmul` extension (`M` sub-extension) available when set (via top's <<_cpu_extension_riscv_zmmul>> generic)
|
|
| 1 | _CSR_MXISA_ZIFENCEI_ | r/- | `Zifencei` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zifencei>> generic)
|
|
| 0 | _CSR_MXISA_ZICSR_ | r/- | `Zicsr` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zicsr>> generic)
|
|
|=======================
|
