| Line 83... |
Line 83... |
| 0x341 | <<_mepc>> | _CSR_MEPC_ | r/w | Machine exception program counter |
|
| 0x341 | <<_mepc>> | _CSR_MEPC_ | r/w | Machine exception program counter |
|
| 0x342 | <<_mcause>> | _CSR_MCAUSE_ | r/w | Machine trap cause | `X`
|
| 0x342 | <<_mcause>> | _CSR_MCAUSE_ | r/w | Machine trap cause | `X`
|
| 0x343 | <<_mtval>> | _CSR_MTVAL_ | r/- | Machine bad address or instruction | `R`
|
| 0x343 | <<_mtval>> | _CSR_MTVAL_ | r/- | Machine bad address or instruction | `R`
|
| 0x344 | <<_mip>> | _CSR_MIP_ | r/w | Machine interrupt pending register | `X`
|
| 0x344 | <<_mip>> | _CSR_MIP_ | r/w | Machine interrupt pending register | `X`
|
6+^| **<<_machine_physical_memory_protection_csrs>>**
|
6+^| **<<_machine_physical_memory_protection_csrs>>**
|
| 0x3a0 .. 0x3af | <<_pmpcfg, `pmpcfg0`>> .. <<_pmpcfg, `pmpcfg15`>> | _CSR_PMPCFG0_ .. _CSR_PMPCFG15_ | r/w | Physical memory protection config. for region 0..63 | `C`
|
| 0x3a0 .. 0x3af | <<_pmpcfg, `pmpcfg0`>> .. <<_pmpcfg, `pmpcfg3`>> | _CSR_PMPCFG0_ .. _CSR_PMPCFG3_ | r/w | Physical memory protection config. for region 0..15 | `C`
|
| 0x3b0 .. 0x3ef | <<_pmpaddr, `pmpaddr0`>> .. <<_pmpaddr, `pmpaddr63`>> | _CSR_PMPADDR0_ .. _CSR_PMPADDR63_ | r/w | Physical memory protection addr. register region 0..63 |
|
| 0x3b0 .. 0x3ef | <<_pmpaddr, `pmpaddr0`>> .. <<_pmpaddr, `pmpaddr15`>> | _CSR_PMPADDR0_ .. _CSR_PMPADDR15_ | r/w | Physical memory protection addr. register region 0..15 |
|
6+^| **<<_machine_counter_and_timer_csrs>>**
|
6+^| **<<_machine_counter_and_timer_csrs>>**
|
| 0xb00 | <<_mcycleh, `mcycle`>> | _CSR_MCYCLE_ | r/w | Machine cycle counter low word |
|
| 0xb00 | <<_mcycleh, `mcycle`>> | _CSR_MCYCLE_ | r/w | Machine cycle counter low word |
|
| 0xb02 | <<_minstreth, `minstret`>> | _CSR_MINSTRET_ | r/w | Machine instruction-retired counter low word |
|
| 0xb02 | <<_minstreth, `minstret`>> | _CSR_MINSTRET_ | r/w | Machine instruction-retired counter low word |
|
| 0xb80 | <<_mcycleh>> | _CSR_MCYCLE_ | r/w | Machine cycle counter high word |
|
| 0xb80 | <<_mcycleh>> | _CSR_MCYCLE_ | r/w | Machine cycle counter high word |
|
| 0xb82 | <<_minstreth>> | _CSR_MINSTRET_ | r/w | Machine instruction-retired counter high word |
|
| 0xb82 | <<_minstreth>> | _CSR_MINSTRET_ | r/w | Machine instruction-retired counter high word |
|
| Line 218... |
Line 218... |
.Machine status register
|
.Machine status register
|
[cols="^1,<3,^1,<5"]
|
[cols="^1,<3,^1,<5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Bit | Name [C] | R/W | Function
|
| Bit | Name [C] | R/W | Function
|
| 12:11 | _CSR_MSTATUS_MPP_H_ : _CSR_MSTATUS_MPP_L_ | r/w | Previous machine privilege level, 11 = machine (M) level, 00 = user (U) level
|
| 21 | _CSR_MSTATUS_TW_ | r/w | **TW**: Disallows execution of `wfi` instruction in user mode when set; hardwired to zero if user-mode not implemented
|
| 7 | _CSR_MSTATUS_MPIE_ | r/w | Previous machine global interrupt enable flag state
|
| 12:11 | _CSR_MSTATUS_MPP_H_ : _CSR_MSTATUS_MPP_L_ | r/w | **MPP*: Previous machine privilege level, 11 = machine (M) level, 00 = user (U) level
|
| 3 | _CSR_MSTATUS_MIE_ | r/w | Machine global interrupt enable flag
|
| 7 | _CSR_MSTATUS_MPIE_ | r/w | **MPIE**: Previous machine global interrupt enable flag state
|
|
| 3 | _CSR_MSTATUS_MIE_ | r/w | **MIE**: Machine global interrupt enable flag
|
|=======================
|
|=======================
|
|
|
When entering an exception/interrupt, the `MIE` flag is copied to `MPIE` and cleared afterwards. When leaving
|
When entering an exception/interrupt, the `MIE` flag is copied to `MPIE` and cleared afterwards. When leaving
|
the exception/interrupt (via the `mret` instruction), `MPIE` is copied back to `MIE`.
|
the exception/interrupt (via the `mret` instruction), `MPIE` is copied back to `MIE`.
|
|
|
| Line 249... |
Line 250... |
.Machine ISA and extension register
|
.Machine ISA and extension register
|
[cols="^1,<3,^1,<5"]
|
[cols="^1,<3,^1,<5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Bit | Name [C] | R/W | Function
|
| Bit | Name [C] | R/W | Function
|
| 31:30 | _CSR_MISA_MXL_HI_EXT_ : _CSR_MISA_MXL_LO_EXT_ | r/- | 32-bit architecture indicator (always _01_)
|
| 31:30 | _CSR_MISA_MXL_HI_EXT_ : _CSR_MISA_MXL_LO_EXT_ | r/- | **MXL**: 32-bit architecture indicator (always _01_)
|
| 23 | _CSR_MISA_X_EXT_ | r/- | `X` extension bit is always set to indicate custom non-standard extensions
|
| 23 | _CSR_MISA_X_EXT_ | r/- | **X**: extension bit is always set to indicate custom non-standard extensions
|
| 20 | _CSR_MISA_U_EXT_ | r/- | `U` CPU extension (user mode) available, set when _CPU_EXTENSION_RISCV_U_ enabled
|
| 20 | _CSR_MISA_U_EXT_ | r/- | **U**: CPU extension (user mode) available, set when _CPU_EXTENSION_RISCV_U_ enabled
|
| 12 | _CSR_MISA_M_EXT_ | r/- | `M` CPU extension (mul/div) available, set when _CPU_EXTENSION_RISCV_M_ enabled
|
| 12 | _CSR_MISA_M_EXT_ | r/- | **M**: CPU extension (mul/div) available, set when _CPU_EXTENSION_RISCV_M_ enabled
|
| 8 | _CSR_MISA_I_EXT_ | r/- | `I` CPU base ISA, cleared when _CPU_EXTENSION_RISCV_E_ enabled
|
| 8 | _CSR_MISA_I_EXT_ | r/- | **I**: CPU base ISA, cleared when _CPU_EXTENSION_RISCV_E_ enabled
|
| 4 | _CSR_MISA_E_EXT_ | r/- | `E` CPU extension (embedded) available, set when _CPU_EXTENSION_RISCV_E_ enabled
|
| 4 | _CSR_MISA_E_EXT_ | r/- | **E**: CPU extension (embedded) available, set when _CPU_EXTENSION_RISCV_E_ enabled
|
| 2 | _CSR_MISA_C_EXT_ | r/- | `C` CPU extension (compressed instruction) available, set when _CPU_EXTENSION_RISCV_C_ enabled
|
| 2 | _CSR_MISA_C_EXT_ | r/- | **C**: CPU extension (compressed instruction) available, set when _CPU_EXTENSION_RISCV_C_ enabled
|
| 0 | _CSR_MISA_A_EXT_ | r/- | `A` CPU extension (atomic memory access) available, set when _CPU_EXTENSION_RISCV_A_ enabled
|
| 0 | _CSR_MISA_A_EXT_ | r/- | **A**: CPU extension (atomic memory access) available, set when _CPU_EXTENSION_RISCV_A_ enabled
|
|=======================
|
|=======================
|
|
|
[TIP]
|
[TIP]
|
Machine-mode software can discover available `Z*` _sub-extensions_ (like `Zicsr` or `Zfinx`) by checking the NEORV32-specific
|
Machine-mode software can discover available `Z*` _sub-extensions_ (like `Zicsr` or `Zfinx`) by checking the NEORV32-specific
|
<<_mxisa>> CSR.
|
<<_mxisa>> CSR.
|
| Line 284... |
Line 285... |
[cols="^1,<3,^1,<5"]
|
[cols="^1,<3,^1,<5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Bit | Name [C] | R/W | Function
|
| Bit | Name [C] | R/W | Function
|
| 31:16 | _CSR_MIE_FIRQ15E_ : _CSR_MIE_FIRQ0E_ | r/w | Fast interrupt channel 15..0 enable
|
| 31:16 | _CSR_MIE_FIRQ15E_ : _CSR_MIE_FIRQ0E_ | r/w | Fast interrupt channel 15..0 enable
|
| 11 | _CSR_MIE_MEIE_ | r/w | Machine _external_ interrupt enable
|
| 11 | _CSR_MIE_MEIE_ | r/w | **MEIE**: Machine _external_ interrupt enable
|
| 7 | _CSR_MIE_MTIE_ | r/w | Machine _timer_ interrupt enable (from _MTIME_)
|
| 7 | _CSR_MIE_MTIE_ | r/w | **MTIE**: Machine _timer_ interrupt enable (from _MTIME_)
|
| 3 | _CSR_MIE_MSIE_ | r/w | Machine _software_ interrupt enable
|
| 3 | _CSR_MIE_MSIE_ | r/w | **MSIE**: Machine _software_ interrupt enable
|
|=======================
|
|=======================
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`mtvec`**
|
===== **`mtvec`**
|
| Line 308... |
Line 309... |
.Machine trap-handler base address
|
.Machine trap-handler base address
|
[cols="^1,^1,<8"]
|
[cols="^1,^1,<8"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Bit | R/W | Function
|
| Bit | R/W | Function
|
| 31:2 | r/w | 4-byte aligned base address of trap base handler
|
| 31:2 | r/w | **BASE**: 4-byte aligned base address of trap base handler
|
| 1:0 | r/- | Always zero
|
| 1:0 | r/- | **MODE**: Always zero; BASE defined entry for _all_ traps
|
|=======================
|
|=======================
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`mcounteren`**
|
===== **`mcounteren`**
|
| Line 333... |
Line 334... |
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|
[cols="^1,<3,^1,<5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Bit | Name [C] | R/W | Function
|
| Bit | Name [C] | R/W | Function
|
| 31:3 | `0` | r/- | Always zero: user-level code is **not** allowed to read HPM counters
|
| 31:3 | `0` | r/- | Always zero: user-level code is **not** allowed to read HPM counters
|
| 2 | _CSR_MCOUNTEREN_IR_ | r/w | User-level code is allowed to read `cycle[h]` CSRs when set
|
| 2 | _CSR_MCOUNTEREN_IR_ | r/w | **IR**: User-level code is allowed to read `cycle[h]` CSRs when set
|
| 1 | _CSR_MCOUNTEREN_TM_ | r/w | User-level code is allowed to read `time[h]` CSRs when set
|
| 1 | _CSR_MCOUNTEREN_TM_ | r/w | **TM**: User-level code is allowed to read `time[h]` CSRs when set
|
| 0 | _CSR_MCOUNTEREN_CY_ | r/w | User-level code is allowed to read `instret[h]` CSRs when set
|
| 0 | _CSR_MCOUNTEREN_CY_ | r/w | **CY**: User-level code is allowed to read `instret[h]` CSRs when set
|
|=======================
|
|=======================
|
|
|
|
.HPM Access
|
|
[NOTE]
|
|
Bits 3 to 31 are used to control user-level access to the <<_hardware_performance_monitors_hpm_csrs>>. In the NEORV32
|
|
CPU these bits are hardwired to zero. Hence, user-level software cannot access the HPMs. Accordingly, the
|
|
`pmcounter*[h]` CSRs are **not** implemented and any access will raise an illegal instruction exception.
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`mstatush`**
|
===== **`mstatush`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
| Line 351... |
Line 358... |
3+| Reset value: _0x00000000_
|
3+| Reset value: _0x00000000_
|
3+| The `mstatush` CSR is compatible to the RISC-V specifications. In combination with <<_mstatus>> it shows additional
|
3+| The `mstatush` CSR is compatible to the RISC-V specifications. In combination with <<_mstatus>> it shows additional
|
execution state information. The NEORV32 `mstatush` CSR is read-only and all bits are hardwired to zero.
|
execution state information. The NEORV32 `mstatush` CSR is read-only and all bits are hardwired to zero.
|
|=======================
|
|=======================
|
|
|
[NOTE]
|
|
The NEORV32 `mstatush` CSR is not a physical register. All write access are ignored and all read accesses will always
|
|
return zero. However, any access will not raise an illegal instruction exception. The CSR address is implemented
|
|
in order to comply with the RISC-V privilege architecture specs.
|
|
|
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
| Line 404... |
Line 406... |
.Machine trap cause register
|
.Machine trap cause register
|
[cols="^1,^1,<8"]
|
[cols="^1,^1,<8"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Bit | R/W | Function
|
| Bit | R/W | Function
|
| 31 | r/w | `1` if the trap is caused by an interrupt (`0` if the trap is caused by an exception)
|
| 31 | r/w | **Interrupt**: `1` if the trap is caused by an interrupt (`0` if the trap is caused by an exception)
|
| 30:5 | r/- | _Reserved_, read as zero
|
| 30:5 | r/- | _Reserved_, read as zero
|
| 4:0 | r/w | Trap ID, see <<_neorv32_trap_listing>>
|
| 4:0 | r/w | **Trap ID**: see <<_neorv32_trap_listing>>
|
|=======================
|
|=======================
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`mtval`**
|
===== **`mtval`**
|
|
|
| Line 448... |
Line 450... |
| 0x344 | **Machine interrupt Pending** | `mip`
|
| 0x344 | **Machine interrupt Pending** | `mip`
|
3+| Reset value: _0x00000000_
|
3+| Reset value: _0x00000000_
|
3+| The `mip` CSR is compatible to the RISC-V specifications and also provides custom extensions. It shows currently _pending_ interrupts.
|
3+| The `mip` CSR is compatible to the RISC-V specifications and also provides custom extensions. It shows currently _pending_ interrupts.
|
The bits for the standard RISC-V interrupts are read-only. Hence, these interrupts cannot be cleared using the `mip` register and must
|
The bits for the standard RISC-V interrupts are read-only. Hence, these interrupts cannot be cleared using the `mip` register and must
|
be cleared/acknowledged within the according interrupt-generating device.
|
be cleared/acknowledged within the according interrupt-generating device.
|
The upper 16 bits represent the status of the CPU's fast interrupt request lines (FIRQ). Once triggered, these _have to be cleared_ again by setting
|
The upper 16 bits represent the status of the CPU's fast interrupt request lines (FIRQ). Once triggered, these bit have to be cleared manually by
|
the according `mip` bit in the interrupt handler routine to clear the current interrupt request.
|
writing zero to the according `mip` bits (in the interrupt handler routine) to clear the current interrupt request.
|
|=======================
|
|=======================
|
|
|
.Machine interrupt pending register
|
.Machine interrupt pending register
|
[cols="^1,<3,^1,<5"]
|
[cols="^1,<3,^1,<5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Bit | Name [C] | R/W | Function
|
| Bit | Name [C] | R/W | Function
|
| 31:16 | _CSR_MIP_FIRQ15P_ : _CSR_MIP_FIRQ0P_ | r/w | fast interrupt channel 15..0 pending; cleared request by writing 1
|
| 31:16 | _CSR_MIP_FIRQ15P_ : _CSR_MIP_FIRQ0P_ | r/c | **FIRQxP**: Fast interrupt channel 15..0 pending; cleared request by writing 1
|
| 11 | _CSR_MIP_MEIP_ | r/- | machine _external_ interrupt pending; _cleared by user-defined mechanism_
|
| 11 | _CSR_MIP_MEIP_ | r/- | **MEIP**: Machine _external_ interrupt pending; _cleared by user-defined mechanism_
|
| 7 | _CSR_MIP_MTIP_ | r/- | machine _timer_ interrupt pending; cleared by incrementing MTIME's time compare register
|
| 7 | _CSR_MIP_MTIP_ | r/- | **MTIP**: Machine _timer_ interrupt pending; cleared by incrementing MTIME's time compare register
|
| 3 | _CSR_MIP_MSIP_ | r/- | machine _software_ interrupt pending; _cleared by user-defined mechanism_
|
| 3 | _CSR_MIP_MSIP_ | r/- | **MSIP**: Machine _software_ interrupt pending; _cleared by user-defined mechanism_
|
|=======================
|
|=======================
|
|
|
|
.FIRQ Channel Mapping
|
|
[TIP]
|
|
See section <<_neorv32_specific_fast_interrupt_requests>> for the mapping of the FIRQ channels and the according
|
|
interrupt-triggering processor module.
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== Machine Physical Memory Protection CSRs
|
==== Machine Physical Memory Protection CSRs
|
|
|
The available physical memory protection logic is configured via the _PMP_NUM_REGIONS_ and
|
The available physical memory protection logic is configured via the <<_pmp_num_regions>> and
|
_PMP_MIN_GRANULARITY_ top entity generics. _PMP_NUM_REGIONS_ defines the number of implemented
|
<<_pmp_min_granularity>> top entity generics. <<_pmp_num_regions>> defines the number of implemented
|
protection regions and thus, the availability of the according `pmpcfg*` and `pmpaddr*` CSRs.
|
protection regions and thus, the implementation of the available _PMP entries_. Each PMP entry consists of an
|
|
8-bit `pmpcfg` CSR entry and a complete `pmpaddr*` CSR.
|
|
See section <<_pmp_physical_memory_protection>> for more information.
|
|
|
[NOTE]
|
[NOTE]
|
If trying to access an PMP-related CSR beyond _PMP_NUM_REGIONS_ **no illegal instruction
|
If trying to access an PMP-related CSR beyond <<_pmp_num_regions>> **no illegal instruction
|
exception** is triggered. The according CSRs are read-only (writes are ignored) and always return zero.
|
exception** is triggered. The according CSRs are read-only (writes are ignored) and always return zero.
|
|
However, any access beyond `pmpcfg3` or `pmpaddr15`, which are the last physically implemented registers if
|
[IMPORTANT]
|
<<_pmp_num_regions>> == 16, will raise an illegal instruction exception as these CSRs are not implemented at all.
|
The RISC-V-compatible NEORV32 physical memory protection only implements the **NAPOT**
|
|
(naturally aligned power-of-two region) mode yet with a minimal region granularity of 8 bytes.
|
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`pmpcfg`**
|
===== **`pmpcfg`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|=======================
|
|=======================
|
| 0x3a0 - 0x3af| **Physical memory protection configuration registers** | `pmpcfg0` - `pmpcfg15`
|
| 0x3a0 - 0x3a3| **Physical memory protection configuration registers** | `pmpcfg0` - `pmpcfg3`
|
3+| Reset value: _0x00000000_
|
3+| Reset value: _0x00000000_
|
3+| The `pmpcfg*` CSRs are compatible to the RISC-V specifications. They are used to configure the protected
|
3+| The `pmpcfg*` CSRs are compatible to the RISC-V specifications. They are used to configure the protected
|
regions, where each `pmpcfg*` CSR provides configuration bits for four regions. The following bits (for the
|
regions, where each `pmpcfg*` CSR provides configuration bits for four regions (8-bit per region).
|
first PMP configuration entry) are implemented (all remaining bits are always zero and are read-only):
|
The actual number of available `pmpcfg` CSRs and CSR entries is defined by the <<_pmp_num_regions>> generic.
|
|=======================
|
|=======================
|
|
|
.Physical memory protection configuration register entry
|
.Physical memory protection configuration register layout (1 entry out of 4)
|
[cols="^1,^3,^1,<11"]
|
[cols="^1,^3,^1,<11"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Bit | RISC-V name | R/W | Function
|
| Bit | Name [C] | R/W | Function
|
| 7 | _L_ | r/w | lock bit, can only be cleared by CPU reset
|
| 7 | _PMPCFG_L_ | r/w | **L**: Lock bit, prevents further write accesses, also enforces access rights in machine-mode, can only be cleared by CPU reset
|
| 6:5 | - | r/- | reserved, read as zero
|
| 6:5 | - | r/- | _reserved_, read as zero
|
| 4:3 | _A_ | r/w | mode configuration; only OFF (`00`) and NAPOT (`11`) are supported
|
| 4 | _PMPCFG_A_MSB_ | r/- .2+<| **A**: Mode configuration; only **OFF** (`00`) and **TOR** (`01`) modes are supported, any other value will map back to OFF/TOR
|
| 2 | _X_ | r/w | execute permission
|
as the MSB is hardwired to zero
|
| 1 | _W_ | r/w | write permission
|
| 3 | _PMPCFG_A_LSB_ | r/w
|
| 0 | _R_ | r/w | read permission
|
| 2 | _PMPCFG_X_ | r/w | **X**: Execute permission
|
|
| 1 | _PMPCFG_W_ | r/w | **W**: Write permission
|
|
| 0 | _PMPCFG_R_ | r/w | **R**: Read permission
|
|=======================
|
|=======================
|
|
|
|
[WARNING]
|
|
Setting the lock bit `L` **only locks the according PMP entry** and not the PMP entries below!
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== **`pmpaddr`**
|
===== **`pmpaddr`**
|
|
|
[cols="4,27,>7"]
|
[cols="4,27,>7"]
|
[frame="topbot",grid="none"]
|
[frame="topbot",grid="none"]
|
|=======================
|
|=======================
|
| 0x3b0 - 0x3ef| **Physical memory protection address registers** | `pmpaddr0` - `pmpaddr63`
|
| 0x3b0 - 0x3bf| **Physical memory protection address registers** | `pmpaddr0` - `pmpaddr15`
|
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `pmpaddr*` CSRs are compatible to the RISC-V specifications. They are used to configure the PMP region's base
|
3+| The `pmpaddr*` CSRs are compatible to the RISC-V specifications. They are used to configure bits 33:2 of the PMP region's
|
address and the region size.
|
physical memory address. The actual number of available `pmpaddr` CSRs is defined by the <<_pmp_num_regions>> generic.
|
|
|=======================
|
|
|
|
.Physical memory protection address register layout
|
|
[cols="^6,^3,<7"]
|
|
[options="header",grid="rows"]
|
|
|=======================
|
|
| Bit | R/W | Function
|
|
| 31:30 | r/- | Hardwired to zero
|
|
| 29 : _log2(PMP_MIN_GRANULARITY)-2_ | r/w | Bits 31 downto _log2(PMP_MIN_GRANULARITY)_ of the region's address
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|
| _log2(PMP_MIN_GRANULARITY)-2_ : 0 | r/- | Hardwired to zero
|
|=======================
|
|=======================
|
|
|
[NOTE]
|
[NOTE]
|
When configuring PMP make sure to set `pmpaddr*` before activating the according region via
|
When configuring the PMP make sure to set `pmpaddr*` before activating the according region via
|
`pmpcfg*`. When changing the PMP configuration, deactivate the according region via `pmpcfg*`
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`pmpcfg*`. When changing the PMP configuration, deactivate the according region via `pmpcfg*`
|
before modifying `pmpaddr*`.
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before modifying `pmpaddr*`.
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|
|
|
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| Line 651... |
Line 673... |
|
|
[TIP]
|
[TIP]
|
If trying to access an HPM-related CSR beyond <<_hpm_num_cnts>> **no illegal instruction exception is
|
If trying to access an HPM-related CSR beyond <<_hpm_num_cnts>> **no illegal instruction exception is
|
triggered**. The according CSRs are read-only (writes are ignored) and always return zero.
|
triggered**. The according CSRs are read-only (writes are ignored) and always return zero.
|
|
|
[IMPORTANT]
|
[NOTE]
|
The HPM system only allows machine-mode access. Hence, `hpmcounter*[h]` CSR are not implemented
|
The HPM system only allows machine-mode access. Hence, `hpmcounter*[h]` CSR are not implemented
|
and any access (even) from machine mode will raise an exception. Furthermore, the according bits of <<_mcounteren>>
|
and any access (even) from machine mode will raise an exception. Furthermore, the according bits of <<_mcounteren>>
|
used to configure user-mode access to `hpmcounter*[h]` are hard-wired to zero.
|
used to configure user-mode access to `hpmcounter*[h]` are hard-wired to zero.
|
|
|
The total counter width of the HPMs can be configured before synthesis via the <<_hpm_cnt_width>> generic (0..64-bit).
|
The total counter width of the HPMs can be configured before synthesis via the <<_hpm_cnt_width>> generic (0..64-bit).
|
| Line 682... |
Line 704... |
3+| Reset value: _UNDEFINED_
|
3+| Reset value: _UNDEFINED_
|
3+| The `mhpmevent*` CSRs are compatible to the RISC-V specifications. The configuration of these CSR define
|
3+| The `mhpmevent*` CSRs are compatible to the RISC-V specifications. The configuration of these CSR define
|
the architectural events that cause the according `mhpmcounter*[h]` counters to increment. All available events are
|
the architectural events that cause the according `mhpmcounter*[h]` counters to increment. All available events are
|
listed in the table below. If more than one event is selected, the according counter will increment if any of
|
listed in the table below. If more than one event is selected, the according counter will increment if any of
|
the enabled events is observed (logical OR). Note that the counter will only increment by 1 step per clock
|
the enabled events is observed (logical OR). Note that the counter will only increment by 1 step per clock
|
cycle even if more than one event is observed. If the CPU is in sleep mode, no HPM counter will increment
|
cycle even if more than one event is observed. If the CPU is in sleep or debug mode, no HPM counter will increment
|
at all.
|
at all.
|
|=======================
|
|=======================
|
|
|
The available hardware performance logic is configured via the _HPM_NUM_CNTS_ top entity generic.
|
|
_HPM_NUM_CNTS_ defines the number of implemented performance monitors and thus, the availability of the
|
|
according `mhpmcounter*[h]` and `mhpmevent*` CSRs.
|
|
|
|
.HPM event selector
|
.HPM event selector
|
[cols="^1,<3,^1,<5"]
|
[cols="^1,<3,^1,<5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Bit | Name [C] | R/W | Event
|
| Bit | Name [C] | R/W | Event
|
| 0 | _HPMCNT_EVENT_CY_ | r/w | active clock cycle (not in sleep)
|
| 0 | _HPMCNT_EVENT_CY_ | r/w | active clock cycle (not in sleep)
|
| 1 | - | r/- | _not implemented, always read as zero_
|
| 1 | - | r/- | _not implemented, always read as zero_
|
| 2 | _HPMCNT_EVENT_IR_ | r/w | retired instruction
|
| 2 | _HPMCNT_EVENT_IR_ | r/w | retired instruction (compressed or uncompressed)
|
| 3 | _HPMCNT_EVENT_CIR_ | r/w | retired compressed instruction
|
| 3 | _HPMCNT_EVENT_CIR_ | r/w | retired compressed instruction
|
| 4 | _HPMCNT_EVENT_WAIT_IF_ | r/w | instruction fetch memory wait cycle (if more than 1 cycle memory latency)
|
| 4 | _HPMCNT_EVENT_WAIT_IF_ | r/w | instruction fetch memory wait cycle (if more than 1 cycle memory latency)
|
| 5 | _HPMCNT_EVENT_WAIT_II_ | r/w | instruction issue pipeline wait cycle (if more than 1 cycle latency), caused by pipelines flushes (like taken branches)
|
| 5 | _HPMCNT_EVENT_WAIT_II_ | r/w | instruction issue pipeline wait cycle (if more than 1 cycle latency), caused by pipelines flushes (like taken branches)
|
| 6 | _HPMCNT_EVENT_WAIT_MC_ | r/w | multi-cycle ALU operation wait cycle
|
| 6 | _HPMCNT_EVENT_WAIT_MC_ | r/w | multi-cycle ALU operation wait cycle
|
| 7 | _HPMCNT_EVENT_LOAD_ | r/w | load operation
|
| 7 | _HPMCNT_EVENT_LOAD_ | r/w | memory data load operation
|
| 8 | _HPMCNT_EVENT_STORE_ | r/w | store operation
|
| 8 | _HPMCNT_EVENT_STORE_ | r/w | memory data store operation
|
| 9 | _HPMCNT_EVENT_WAIT_LS_ | r/w | load/store memory wait cycle (if more than 1 cycle memory latency)
|
| 9 | _HPMCNT_EVENT_WAIT_LS_ | r/w | load/store memory wait cycle (if more than 1 cycle memory latency)
|
| 10 | _HPMCNT_EVENT_JUMP_ | r/w | unconditional jump
|
| 10 | _HPMCNT_EVENT_JUMP_ | r/w | unconditional jump
|
| 11 | _HPMCNT_EVENT_BRANCH_ | r/w | conditional branch (taken or not taken)
|
| 11 | _HPMCNT_EVENT_BRANCH_ | r/w | conditional branch (taken or not taken)
|
| 12 | _HPMCNT_EVENT_TBRANCH_ | r/w | taken conditional branch
|
| 12 | _HPMCNT_EVENT_TBRANCH_ | r/w | taken conditional branch
|
| 13 | _HPMCNT_EVENT_TRAP_ | r/w | entered trap
|
| 13 | _HPMCNT_EVENT_TRAP_ | r/w | entered trap (synchronous exception or interrupt)
|
| 14 | _HPMCNT_EVENT_ILLEGAL_ | r/w | illegal instruction exception
|
| 14 | _HPMCNT_EVENT_ILLEGAL_ | r/w | illegal instruction exception
|
|=======================
|
|=======================
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
| Line 752... |
Line 770... |
.Machine counter-inhibit register
|
.Machine counter-inhibit register
|
[cols="^1,<3,^1,<5"]
|
[cols="^1,<3,^1,<5"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Bit | Name [C] | R/W | Event
|
| Bit | Name [C] | R/W | Event
|
| 0 | _CSR_MCOUNTINHIBIT_IR_ | r/w | the `[m]instret[h]` CSRs will auto-increment with each committed instruction when set
|
| 0 | _CSR_MCOUNTINHIBIT_IR_ | r/w | **IR**: The `[m]instret[h]` CSRs will auto-increment with each committed instruction when set
|
| 2 | _CSR_MCOUNTINHIBIT_IR_ | r/w | the `[m]cycle[h]` CSRs will auto-increment with each clock cycle (if CPU is not in sleep state) when set
|
| 2 | _CSR_MCOUNTINHIBIT_CY_ | r/w | **CY**: The `[m]cycle[h]` CSRs will auto-increment with each clock cycle (if CPU is not in sleep state) when set
|
| 3:31 | _CSR_MCOUNTINHIBIT_HPM3_ _: _CSR_MCOUNTINHIBIT_HPM31_ | r/w | the `mhpmcount*[h]` CSRs will auto-increment according to the configured `mhpmevent*` selector
|
| 3:31 | _CSR_MCOUNTINHIBIT_HPM3_ : _CSR_MCOUNTINHIBIT_HPM31_ | r/w | **HPMx**: The `mhpmcount*[h]` CSRs will auto-increment according to the configured `mhpmevent*` selector
|
|=======================
|
|=======================
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
