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[/] [neorv32/] [trunk/] [docs/] [datasheet/] [index.adoc] - Diff between revs 60 and 61

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`= The NEORV32 RISC-V Processor: Datasheet`	`= The NEORV32 RISC-V Processor: Datasheet`
	`include::../attrs.adoc[]`
`:title: [Datasheet] The NEORV32 RISC-V Processor`	`:title: [Datasheet] The NEORV32 RISC-V Processor`
`:author: Dipl.-Ing. Stephan Nolting`
`:email: stnolting@gmail.com`
`:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.`
`:revnumber: v1.5.6.0`
`:doctype: book`
`:sectnums:`
`:icons: font`	`:icons: font`
`:imagesdir: img`	`:imagesdir: img`
`:stem:`
`:reproducible:`
`:listing-caption: Listing`
`:toc: left`	`:toc: left`
`:toclevels: 4`
`:title-logo-image: neorv32_logo_dark.png[pdfwidth=6.25in,align=center]`	`:title-logo-image: neorv32_logo_dark.png[pdfwidth=6.25in,align=center]`
`:favicon: img/icon.png`	`:favicon: img/icon.png`

`image::neorv32_logo_transparent.png[align=center]`	`image::neorv32_logo_transparent.png[align=center]`