| Line 14... |
Line 14... |
* accessing core registers (direct access to GPRs, indirect access to CSRs via program buffer)
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* accessing core registers (direct access to GPRs, indirect access to CSRs via program buffer)
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* indirect access to the whole processor address space (via program buffer))
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* indirect access to the whole processor address space (via program buffer))
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* compatible to the https://github.com/riscv/riscv-openocd[RISC-V port of OpenOCD];
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* compatible to the https://github.com/riscv/riscv-openocd[RISC-V port of OpenOCD];
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pre-built binaries can be obtained for example from https://www.sifive.com/software[SiFive]
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pre-built binaries can be obtained for example from https://www.sifive.com/software[SiFive]
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.OCD Security Note
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|
[IMPORTANT]
|
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Access via the OCD is _always authenticated_ (`dmstatus.authenticated` == `1`). Hence, the
|
|
_whole system_ can always be accessed via the on-chip debugger.
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[NOTE]
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[NOTE]
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The OCD requires additional resources for implementation and _might_ also increase the critical path resulting in less
|
The OCD requires additional resources for implementation and _might_ also increase the critical path resulting in less
|
performance. If the OCD is not really required for the _final_ implementation, it can be disabled and thus,
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performance. If the OCD is not really required for the _final_ implementation, it can be disabled and thus,
|
discarded from implementation. In this case all circuitry of the debugger is completely removed (no impact
|
discarded from implementation. In this case all circuitry of the debugger is completely removed (no impact
|
on area, energy or timing at all).
|
on area, energy or timing at all).
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| Line 63... |
Line 68... |
=== Debug Transport Module (DTM)
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=== Debug Transport Module (DTM)
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|
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The debug transport module (VHDL module: `rtl/core/neorv32_debug_dtm.vhd`) provides a JTAG test access port (TAP).
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The debug transport module (VHDL module: `rtl/core/neorv32_debug_dtm.vhd`) provides a JTAG test access port (TAP).
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The DTM is the first entity in the debug system, which connects and external debugger via JTAG to the next debugging
|
The DTM is the first entity in the debug system, which connects and external debugger via JTAG to the next debugging
|
entity: the debug module (DM).
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entity: the debug module (DM).
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External access is provided by the following top-level ports.
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External JTAG access is provided by the following top-level ports.
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.JTAG top level signals
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.JTAG top level signals
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[cols="^2,^2,^2,<8"]
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[cols="^2,^2,^2,<8"]
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
|
