| Line 1... |
Line 1... |
:sectnums:
|
:sectnums:
|
== Overview
|
== Overview
|
|
|
[quote]
|
|
____
|
|
RISC-V - Instruction Sets Want To Be Free!
|
|
____
|
|
|
|
The NEORV32footnote:[Pronounced "neo-R-V-thirty-two" or "neo-risc-five-thirty-two" in its long form.] is an open-source
|
The NEORV32footnote:[Pronounced "neo-R-V-thirty-two" or "neo-risc-five-thirty-two" in its long form.] is an open-source
|
RISC-V compatible processor system that is intended as *ready-to-go* auxiliary processor within a larger SoC
|
RISC-V compatible processor system that is intended as *ready-to-go* auxiliary processor within a larger SoC
|
designs or as stand-alone custom / customizable microcontroller.
|
designs or as stand-alone custom / customizable microcontroller.
|
|
|
The system is highly configurable and provides optional common peripherals like embedded memories,
|
The system is highly configurable and provides optional common peripherals like embedded memories,
|
| Line 19... |
Line 14... |
and processor features, a bootloader, a runtime environment and several example programs – including a port
|
and processor features, a bootloader, a runtime environment and several example programs – including a port
|
of the CoreMark MCU benchmark and the official RISC-V architecture test suite. RISC-V GCC is used as
|
of the CoreMark MCU benchmark and the official RISC-V architecture test suite. RISC-V GCC is used as
|
default toolchain (https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt toolchains are also provided]).
|
default toolchain (https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt toolchains are also provided]).
|
|
|
[TIP]
|
[TIP]
|
|
Check out the processor's **https://stnolting.github.io/neorv32/ug[online User Guide]**
|
|
that provides hands-on tutorial to get you started.
|
|
|
|
[TIP]
|
The project's change log is available in https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md[CHANGELOG.md]
|
The project's change log is available in https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md[CHANGELOG.md]
|
in the root directory of the NEORV32 repository. Please also check out the <<_legal>> section.
|
in the root directory of the NEORV32 repository. Please also check out the <<_legal>> section.
|
|
|
|
|
|
**Structure**
|
|
|
:sectnums!:
|
* <<_neorv32_processor_soc>>
|
=== Structure
|
* <<_neorv32_central_processing_unit_cpu>>
|
|
* <<_on_chip_debugger_ocd>>
|
|
* <<_software_framework>>
|
|
|
Chapter <<_neorv32_processor_soc>>
|
[TIP]
|
|
Links in this document are <<_overview,highlighted>>.
|
|
|
* top entity signals and configuration generics, address space layout, internal peripheral devices and interrupts, internal
|
|
memories and caches, internal bus architecture, external bus interface
|
|
|
|
Chapter <<_neorv32_central_processing_unit_cpu>>
|
|
|
|
* instruction set(s) and extensions, instruction timing, control ans status registers, traps, exceptions and interrupts,
|
|
hardware execution safety, native bus interface
|
// ####################################################################################################################
|
|
:sectnums:
|
|
=== Rationale
|
|
|
Chapter <<_on_chip_debugger_ocd>>
|
**Why did you make this?**
|
|
|
* on-chip debugging compatible to the "Minimal RISC-V Debug Specification Version 0.13.2".
|
I am fascinated by processor and CPU architecture design: it is the magic frontier where software meets hardware.
|
|
This project has started as something like a _journey_ into this magic realm to understand how things actually work
|
|
down on this very low level.
|
|
|
Chapter <<_software_framework>>
|
But there is more! When I started to dive into the emerging RISC-V ecosystem I felt overwhelmed by the complexity.
|
|
As a beginner it is hard to get an overview - especially when you want to setup a minimal platform to tinker with:
|
|
Which core to use? How to get the right toolchain? What features do I need? How does the booting work? How do I
|
|
create an actual executable? How to get that into the hardware? How to customize things? **_Where to start???_**
|
|
|
* core libraries, bootloader, makefiles, runtime environment
|
So this project aims to provides a _simple to understand_ and _easy to use_ yet _powerful_ and _flexible_ platform
|
|
that targets FPGA and RISC-V beginners as well as advanced users. Join me and us on this journey! 🙃
|
|
|
Chapter <<_lets_get_it_started>>
|
|
|
|
* toolchain installation and setup, hardware setup, software setup, application compilation, simulating the processor
|
**Why a _soft_-core processor?**
|
debugging using the on-chip debugger
|
|
|
|
[TIP]
|
As a matter of fact soft-core processors _cannot_ compete with discrete or FPGA hard-macro processors in terms
|
Links in this document are <<_structure,highlighted>>.
|
of performance, energy and size. But they do fill a niche in FPGA design space. For example, soft-core processors
|
|
allow to implement the _control flow part_ of certain applications (like communication protocol handling) using
|
|
software like plain C. This provides high flexibility as software can be easily changed, re-compiled and
|
|
re-uploaded again.
|
|
|
|
Furthermore, the concept of flexibility applies to all aspects of a soft-core processor. The user can add
|
|
_exactly_ the features that are required by the application: additional memories, custom interfaces, specialized
|
|
IP and even user-defined instructions.
|
|
|
|
|
|
**Why RISC-V?**
|
|
|
|
[quote, RISC-V International, https://riscv.org/about/]
|
|
____
|
|
RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.
|
|
____
|
|
|
|
I love the idea of open-source. **Knowledge can help best if it is freely available.**
|
|
While open-source has already become quite popular in _software_, hardware projects still need to catch up.
|
|
Admittedly, there has been quite a development, but mainly in terms of _platforms_ and _applications_ (so
|
|
schematics, PCBs, etc.). Although processors and CPUs are the heart of almost every digital system, having a true
|
|
open-source silicon is still a rarity. RISC-V aims to change that. Even it is _just one approach_, it helps paving
|
|
the road for future development.
|
|
|
|
Furthermore, I welcome the community aspect of RISC-V. The ISA and everything beyond is developed with direct
|
|
contact to the community: this includes businesses and professionals but also hobbyist, amateurs and people
|
|
that are just curious. Everyone can join discussions and contribute to RISC-V in their very own way.
|
|
|
|
Finally, I really like the RISC-V ISA itself. It aims to be a clean, orthogonal and "intuitive" ISA that
|
|
resembles with the basic concepts of _RISC_: simple yet effective.
|
|
|
|
|
|
**Yet another RISC-V core? What makes it special?**
|
|
|
|
The NEORV32 is not based on another RISC-V core. It was build entirely from ground up (just following the official
|
|
ISA specs) having a different design goal in mind. The project does not intend to replace certain RISC-V cores or
|
|
just beat existing ones like https://github.com/SpinalHDL/VexRiscv[VexRISC] in terms of performance or
|
|
https://github.com/olofk/serv[SERV] in terms of size.
|
|
|
|
The project aims to provide _another option_ in the RISC-V / soft-core design space with a different performance
|
|
vs. size trade-off and a different focus: _embrace_ concepts like documentation, platform-independence / portability,
|
|
RISC-V compatibility, _customization_ and _ease of use_. See the <<_project_key_features>> below.
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
=== Project Key Features
|
=== Project Key Features
|
|
|
* **NEORV32 CPU**: 32-bit `rv32i` RISC-V CPU - passes the official RISC-V architecture tests
|
* open-source and documented; including user guides to get started
|
* official https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md[RISC-V open source architecture ID]
|
* completely described in behavioral, platform-independent VHDL (yet platform-optimized modules are provided)
|
* optional RISC-V CPU extensions:
|
* fully synchronous design, no latches, no gated clocks
|
** `A` - atomic memory access operations
|
* small hardware footprint and high operating frequency for easy integration
|
** `B` - bit-manipulation instructions
|
* **NEORV32 CPU**: 32-bit `rv32i` RISC-V CPU
|
** `C` - 16-bit compressed instructions
|
** RISC-V compatibility: passes the official architecture tests
|
** `E` - embedded CPU version (reduced register file size)
|
** base architecture + privileged architecture (optional) + ISA extensions (optional)
|
** `M` - integer multiplication and division hardware
|
** rich set of customization options (ISA extensions, design goal: performance / area (/ energy), ...)
|
** `U` - less-privileged _user_ mode
|
** official https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md[RISC-V open source architecture ID]
|
** `Zfinx` - single-precision floating-point unit
|
* **NEORV32 Processor (SoC)**: highly-configurable full-scale microcontroller-like processor system
|
** `Zicsr` - control and status register access (privileged architecture)
|
** based on the NEORV32 CPU
|
** `Zifencei` - instruction stream synchronization
|
** optional serial interfaces (UARTs, TWI, SPI)
|
** `PMP` - physical memory protection
|
** optional timers and counters (WDT, MTIME)
|
** `HPM` - hardware performance monitors
|
** optional general purpose IO and PWM and native NeoPixel (c) compatible smart LED interface
|
|
** optional embedded memories / caches for data, instructions and bootloader
|
|
** optional external memory interface (Wishbone / AXI4-Lite) and stream link interface (AXI4-Stream) for custom connectivity
|
|
** on-chip debugger compatible with OpenOCD and gdb
|
* **Software framework**
|
* **Software framework**
|
** GCC-based toolchain - prebuilt toolchains available; application compilation based on GNU makefiles
|
** GCC-based toolchain - prebuilt toolchains available; application compilation based on GNU makefiles
|
** internal bootloader with serial user interface
|
** internal bootloader with serial user interface
|
** core libraries for high-level usage of the provided functions and peripherals
|
** core libraries for high-level usage of the provided functions and peripherals
|
** runtime environment and several example programs
|
** runtime environment and several example programs
|
** doxygen-based documentation of the software framework; a deployed version is available at https://stnolting.github.io/neorv32/sw/files.html
|
** doxygen-based documentation of the software framework; a deployed version is available at https://stnolting.github.io/neorv32/sw/files.html
|
** FreeRTOS port + demos available
|
** FreeRTOS port + demos available
|
* **NEORV32 Processor**: highly-configurable full-scale microcontroller-like processor system / SoC based on the NEORV32 CPU with optional standard peripherals:
|
|
** serial interfaces (UARTs, TWI, SPI)
|
[TIP]
|
** timers and counters (WDT, MTIME, NCO)
|
For more in-depth details regarding the feature provided by he hardware see the according sections:
|
** general purpose IO and PWM and native NeoPixel (c) compatible smart LED interface
|
<<_neorv32_central_processing_unit_cpu>> and <<_neorv32_processor_soc>>.
|
** embedded memories / caches for data, instructions and bootloader
|
|
** external memory interface (Wishbone or AXI4-Lite)
|
|
* on-chip debugger compatible with OpenOCD and gdb
|
|
* fully synchronous design, no latches, no gated clocks
|
|
* completely described in behavioral, platform-independent VHDL
|
|
* small hardware footprint and high operating frequency
|
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
=== Project Folder Structure
|
=== Project Folder Structure
|
|
|
...................................
|
...................................
|
neorv32 - Project home folder
|
neorv32 - Project home folder
|
├.ci - Scripts for continuous integration
|
├.ci - Scripts for continuous integration
|
├boards - Example setups for various FPGA boards
|
├setups - Example setups for various FPGA boards and toolchains
|
|
│└...
|
├CHANGELOG.md - Project change log
|
├CHANGELOG.md - Project change log
|
├docs - Project documentation
|
├docs - Project documentation
|
│├doxygen_build - Software framework documentation (generated by doxygen)
|
│├doxygen_build - Software framework documentation (generated by doxygen)
|
│├src_adoc - AsciiDoc sources for this document
|
│├src_adoc - AsciiDoc sources for this document
|
│├references - Data sheets and RISC-V specs.
|
│├references - Data sheets and RISC-V specs.
|
│└figures - Figures and logos
|
│└figures - Figures and logos
|
├riscv-arch-test - Port files for the official RISC-V architecture tests
|
├riscv-arch-test - Port files for the official RISC-V architecture tests
|
├rtl - VHDL sources
|
├rtl - VHDL sources
|
│├core - Sources of the CPU & SoC
|
│├core - Sources of the CPU & SoC
|
│└top_templates - Alternate/additional top entities/wrappers
|
│└templates - Alternate/additional top entities/wrappers
|
|
│ ├processor - Processor wrappers
|
|
│ └system - System wrappers for advanced connectivity
|
├sim - Simulation files
|
├sim - Simulation files
|
│├ghdl - Simulation scripts for GHDL
|
│└rtl_modules - Processor modules for simulation-only
|
│├rtl_modules - Processor modules for simulation-only
|
|
│└vivado - Pre-configured Xilinx ISIM waveform
|
|
└sw - Software framework
|
└sw - Software framework
|
├bootloader - Sources and scripts for the NEORV32 internal bootloader
|
├bootloader - Sources and scripts for the NEORV32 internal bootloader
|
├common - Linker script and crt0.S start-up code
|
├common - Linker script and crt0.S start-up code
|
├example - Various example programs
|
├example - Various example programs
|
│└...
|
│└...
|
| Line 148... |
Line 191... |
All core VHDL files from the list below have to be assigned to a new design library named **`neorv32`**. Additional
|
All core VHDL files from the list below have to be assigned to a new design library named **`neorv32`**. Additional
|
files, like alternative top entities, can be assigned to any library.
|
files, like alternative top entities, can be assigned to any library.
|
|
|
...................................
|
...................................
|
neorv32_top.vhd - NEORV32 Processor top entity
|
neorv32_top.vhd - NEORV32 Processor top entity
|
|
│
|
|
├neorv32_fifo.vhd - General purpose FIFO component
|
|
├neorv32_package.vhd - Processor/CPU main VHDL package file
|
|
│
|
|
├neorv32_cpu.vhd - NEORV32 CPU top entity
|
|
│├neorv32_cpu_alu.vhd - Arithmetic/logic unit
|
|
││├neorv32_cpu_cp_fpu.vhd - Floating-point co-processor (Zfinx ext.)
|
|
││├neorv32_cpu_cp_muldiv.vhd - Mul/Div co-processor (M extension)
|
|
││└neorv32_cpu_cp_shifter.vhd - Bit-shift co-processor
|
|
│├neorv32_cpu_bus.vhd - Bus interface + physical memory protection
|
|
│├neorv32_cpu_control.vhd - CPU control, exception/IRQ system and CSRs
|
|
││└neorv32_cpu_decompressor.vhd - Compressed instructions decoder
|
|
│└neorv32_cpu_regfile.vhd - Data register file
|
|
│
|
├neorv32_boot_rom.vhd - Bootloader ROM
|
├neorv32_boot_rom.vhd - Bootloader ROM
|
│└neorv32_bootloader_image.vhd - Bootloader boot ROM memory image
|
│└neorv32_bootloader_image.vhd - Bootloader boot ROM memory image
|
├neorv32_busswitch.vhd - Processor bus switch for CPU buses (I&D)
|
├neorv32_busswitch.vhd - Processor bus switch for CPU buses (I&D)
|
├neorv32_bus_keeper.vhd - Processor-internal bus monitor
|
├neorv32_bus_keeper.vhd - Processor-internal bus monitor
|
├neorv32_icache.vhd - Processor-internal instruction cache
|
├neorv32_icache.vhd - Processor-internal instruction cache
|
├neorv32_cfs.vhd - Custom functions subsystem
|
├neorv32_cfs.vhd - Custom functions subsystem
|
├neorv32_cpu.vhd - NEORV32 CPU top entity
|
|
│├neorv32_package.vhd - Processor/CPU main VHDL package file
|
|
│├neorv32_cpu_alu.vhd - Arithmetic/logic unit
|
|
│├neorv32_cpu_bus.vhd - Bus interface unit + physical memory protection
|
|
│├neorv32_cpu_control.vhd - CPU control, exception/IRQ system and CSRs
|
|
││└neorv32_cpu_decompressor.vhd - Compressed instructions decoder
|
|
│├neorv32_cpu_cp_fpu.vhd - Floating-point co-processor (Zfinx extension)
|
|
│├neorv32_cpu_cp_muldiv.vhd - Mul/Div co-processor (M extension)
|
|
│└neorv32_cpu_regfile.vhd - Data register file
|
|
├neorv32_debug_dm.vhd - on-chip debugger: debug module
|
├neorv32_debug_dm.vhd - on-chip debugger: debug module
|
├neorv32_debug_dtm.vhd - on-chip debugger: debug transfer module
|
├neorv32_debug_dtm.vhd - on-chip debugger: debug transfer module
|
├neorv32_dmem.vhd - Processor-internal data memory
|
├neorv32_dmem.vhd - Processor-internal data memory
|
├neorv32_gpio.vhd - General purpose input/output port unit
|
├neorv32_gpio.vhd - General purpose input/output port unit
|
├neorv32_imem.vhd - Processor-internal instruction memory
|
├neorv32_imem.vhd - Processor-internal instruction memory
|
│└neor32_application_image.vhd - IMEM application initialization image
|
│└neor32_application_image.vhd - IMEM application initialization image
|
├neorv32_mtime.vhd - Machine system timer
|
├neorv32_mtime.vhd - Machine system timer
|
├neorv32_nco.vhd - Numerically-controlled oscillator
|
|
├neorv32_neoled.vhd - NeoPixel (TM) compatible smart LED interface
|
├neorv32_neoled.vhd - NeoPixel (TM) compatible smart LED interface
|
├neorv32_pwm.vhd - Pulse-width modulation controller
|
├neorv32_pwm.vhd - Pulse-width modulation controller
|
├neorv32_spi.vhd - Serial peripheral interface controller
|
├neorv32_spi.vhd - Serial peripheral interface controller
|
├neorv32_sysinfo.vhd - System configuration information memory
|
├neorv32_sysinfo.vhd - System configuration information memory
|
├neorv32_trng.vhd - True random number generator
|
├neorv32_trng.vhd - True random number generator
|
├neorv32_twi.vhd - Two wire serial interface controller
|
├neorv32_twi.vhd - Two wire serial interface controller
|
├neorv32_uart.vhd - Universal async. receiver/transmitter
|
├neorv32_uart.vhd - Universal async. receiver/transmitter
|
├neorv32_wdt.vhd - Watchdog timer
|
├neorv32_wdt.vhd - Watchdog timer
|
└neorv32_wb_interface.vhd - External (Wishbone) bus interface
|
├neorv32_wishbone.vhd - External (Wishbone) bus interface
|
|
└neorv32_xirq.vhd - External interrupt controller
|
...................................
|
...................................
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
| Line 206... |
Line 254... |
|
|
[cols="<5,>1,>1,>1,>1,>1"]
|
[cols="<5,>1,>1,>1,>1,>1"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| CPU | LEs | FFs | MEM bits | DSPs | _f~max~_
|
| CPU | LEs | FFs | MEM bits | DSPs | _f~max~_
|
| `rv32i` | 980 | 409 | 1024 | 0 | 123 MHz
|
| `rv32i` | 980 | 409 | 1024 | 0 | 125 MHz
|
| `rv32i_Zicsr` | 1835 | 856 | 1024 | 0 | 124 MHz
|
| `rv32i_Zicsr` | 1835 | 856 | 1024 | 0 | 125 MHz
|
| `rv32im_Zicsr` | 2443 | 1134 | 1024 | 0 | 124 MHz
|
| `rv32im_Zicsr` | 2443 | 1134 | 1024 | 0 | 125 MHz
|
| `rv32imc_Zicsr` | 2669 | 1149 | 1024 | 0 | 125 MHz
|
| `rv32imc_Zicsr` | 2669 | 1149 | 1024 | 0 | 125 MHz
|
| `rv32imac_Zicsr` | 2685 | 1156 | 1024 | 0 | 124 MHz
|
| `rv32imac_Zicsr` | 2685 | 1156 | 1024 | 0 | 125 MHz
|
| `rv32imac_Zicsr` + `debug_mode` | 3058 | 1225 | 1024 | 0 | 120 MHz
|
| `rv32imac_Zicsr` + `debug_mode` | 3058 | 1225 | 1024 | 0 | 125 MHz
|
| `rv32imac_Zicsr` + `u` | 2698 | 1162 | 1024 | 0 | 124 MHz
|
| `rv32imac_Zicsr` + `u` | 2698 | 1162 | 1024 | 0 | 125 MHz
|
| `rv32imac_Zicsr_Zifencei` + `u` | 2715 | 1162 | 1024 | 0 | 122 MHz
|
| `rv32imac_Zicsr_Zifencei` + `u` | 2715 | 1162 | 1024 | 0 | 125 MHz
|
| `rv32imac_Zicsr_Zifencei_Zfinx` + `u` | 4004 | 1812 | 1024 | 7 | 121 MHz
|
| `rv32imac_Zicsr_Zifencei_Zfinx` + `u` | 4004 | 1812 | 1024 | 7 | 118 MHz
|
|=======================
|
|=======================
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Processor Modules
|
==== Processor Modules
|
|
|
[cols="<2,<8"]
|
[cols="<2,<8"]
|
[grid="topbot"]
|
[grid="topbot"]
|
|=======================
|
|=======================
|
| Hardware version: | `1.5.5.9`
|
| Hardware version: | `1.5.7.8`
|
| Top entity: | `rtl/core/neorv32_top.vhd`
|
| Top entity: | `rtl/core/neorv32_top.vhd`
|
|=======================
|
|=======================
|
|
|
.Hardware utilization by the processor modules (mandatory core modules in **bold**)
|
.Hardware utilization by the processor modules (mandatory core modules in **bold**)
|
[cols="<2,<8,>1,>1,>2,>1"]
|
[cols="<2,<8,>1,>1,>2,>1"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Module | Description | LEs | FFs | MEM bits | DSPs
|
| Module | Description | LEs | FFs | MEM bits | DSPs
|
| Boot ROM | Bootloader ROM (4kB) | 3 | 1 | 32768 | 0
|
| Boot ROM | Bootloader ROM (4kB) | 2 | 1 | 32768 | 0
|
| **BUSKEEPER** | Processor-internal bus monitor | 11 | 6 | 0 | 0
|
| **BUSKEEPER** | Processor-internal bus monitor | 9 | 6 | 0 | 0
|
| **BUSSWITCH** | Bus mux for CPU instr. and data interface | 49 | 8 | 0 | 0
|
| **BUSSWITCH** | Bus mux for CPU instr. and data interface | 63 | 8 | 0 | 0
|
| CFS | Custom functions subsystem | - | - | - | -
|
| CFS | Custom functions subsystemfootnote:[Resource utilization depends on actually implemented custom functionality.] | - | - | - | -
|
| DMEM | Processor-internal data memory (8kB) | 18 | 2 | 65536 | 0
|
| DMEM | Processor-internal data memory (8kB) | 19 | 2 | 65536 | 0
|
| DM | On-chip debugger - debug module | 493 | 240 | 0 | 0
|
| DM | On-chip debugger - debug module | 493 | 240 | 0 | 0
|
| DTM | On-chip debugger - debug transfer module (JTAG) | 254 | 218 | 0 | 0
|
| DTM | On-chip debugger - debug transfer module (JTAG) | 254 | 218 | 0 | 0
|
| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0
|
| GPIO | General purpose input/output ports | 134 | 161 | 0 | 0
|
| iCACHE | Instruction cache (1x4 blocks, 256 bytes per block) | 220 | 154 | 8192 | 0
|
| iCACHE | Instruction cache (1x4 blocks, 256 bytes per block) | 2 21| 156 | 8192 | 0
|
| IMEM | Processor-internal instruction memory (16kB) | 6 | 2 | 131072 | 0
|
| IMEM | Processor-internal instruction memory (16kB) | 13 | 2 | 131072 | 0
|
| MTIME | Machine system timer | 289 | 200 | 0 | 0
|
| MTIME | Machine system timer | 319 | 167 | 0 | 0
|
| NCO | Numerically-controlled oscillator | 254 | 226 | 0 | 0
|
| NEOLED | Smart LED Interface (NeoPixel/WS28128) [4xFIFO] | 342 | 307 | 0 | 0
|
| NEOLED | Smart LED Interface (NeoPixel/WS28128) [4xFIFO] | 347 | 309 | 0 | 0
|
| SLINK | Stream link interface (4 links, FIFO_depth=1) | 345 | 313 | 0 | 0
|
| PWM | Pulse_width modulation controller (4 channels) | 71 | 69 | 0 | 0
|
| PWM | Pulse_width modulation controller (4 channels) | 71 | 69 | 0 | 0
|
| SPI | Serial peripheral interface | 138 | 124 | 0 | 0
|
| SPI | Serial peripheral interface | 148 | 127 | 0 | 0
|
| **SYSINFO** | System configuration information memory | 10 | 10 | 0 | 0
|
| **SYSINFO** | System configuration information memory | 14 | 11 | 0 | 0
|
| TRNG | True random number generator | 132 | 105 | 0 | 0
|
| TRNG | True random number generator | 89 | 76 | 0 | 0
|
| TWI | Two-wire interface | 77 | 44 | 0 | 0
|
| TWI | Two-wire interface | 77 | 43 | 0 | 0
|
| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 176 | 132 | 0 | 0
|
| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 183 | 132 | 0 | 0
|
| WDT | Watchdog timer | 60 | 45 | 0 | 0
|
| WDT | Watchdog timer | 53 | 43 | 0 | 0
|
| WISHBONE | External memory interface | 129 | 104 | 0 | 0
|
| WISHBONE | External memory interface | 114 | 110 | 0 | 0
|
|
| XIRQ | External interrupt controller (32 channels) | 241 | 201 | 0 | 0
|
|=======================
|
|=======================
|
|
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Exemplary Setups
|
==== Exemplary Setups
|
|
|
[TIP]
|
[TIP]
|
Exemplary setups for different technologies and various FPGA boards can be found in the `boards` folder
|
Check out the `setups` folder (@GitHub: https://github.com/stnolting/neorv32/tree/master/setups),
|
(https://github.com/stnolting/neorv32/tree/master/boards).
|
which provides several demo setups for various FPGA boards and toolchains.
|
|
|
The following table shows exemplary NEORV32 processor implementation results for different FPGA
|
|
platforms. Most setups use the default peripheral configuration (like no CFS, no caches and no
|
|
TRNG), no external memory interface and only internal instruction and data memories (IMEM uses 16kB
|
|
and DMEM uses 8kB memory space).
|
|
|
|
[cols="<2,<8"]
|
|
[grid="topbot"]
|
|
|=======================
|
|
| Hardware version: | `1.4.9.0`
|
|
|=======================
|
|
|
|
.Hardware utilization for exemplary NEORV32 setups
|
|
[cols="<4,<5,<4,<4,<3,<3,<3,<4,<4,<3"]
|
|
[options="header",grid="rows"]
|
|
|=======================
|
|
| Vendor | FPGA | Board | Toolchain | CPU | LUT | FF | DSP | Memory | _f_
|
|
| Intel | Cyclone IV `EP4CE22F17-C6N` | Terasic DE0-Nano | Quartus Prime Lite 20.1 | `rv32imcu_Zicsr_Zifencei` + `PMP` | 3813 (17%) | 1890 (8%) | 0 (0%) | Memory bits: 231424 (38%) | 119 MHz
|
|
| Lattice | iCE40 UltraPlus `iCE40UP5KSG48I` | Upduino v3.0 | Radiant 2.1 | `rv32icu_Zicsr_Zifencei` | 5123 (97%) | 1972 (37%) | 0 (0%) | EBR: 12 (40%) SPRAM: 4 (100%) | 24 MHz
|
|
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | `rv32imcu_Zicsr_Zifencei` + `PMP` | 2465 (12%) | 1912 (5%) | 0 (0%) | BRAM: 8 (16%) | 100 MHz
|
|
|=======================
|
|
|
|
**Notes**
|
|
|
|
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DEMEM (each 64kB).
|
|
* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32 bootloader to store and automatically boot an application program after reset (both tested successfully).
|
|
* The setups with PMP implement 2 regions with a minimal granularity of 64kB.
|
|
* No HPM counters are used.
|
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
| Line 359... |
Line 380... |
the available CPU extensions. The following table shows the performance results for successfully (!) running
|
the available CPU extensions. The following table shows the performance results for successfully (!) running
|
2000 CoreMark iterations.
|
2000 CoreMark iterations.
|
|
|
The average CPI is computed by dividing the total number of required clock cycles (only the timed core to
|
The average CPI is computed by dividing the total number of required clock cycles (only the timed core to
|
avoid distortion due to IO wait cycles) by the number of executed instructions (`[m]instret[h]` CSRs). The
|
avoid distortion due to IO wait cycles) by the number of executed instructions (`[m]instret[h]` CSRs). The
|
executables were generated using optimization -O3.
|
executables were generated using optimization `-O3`.
|
|
|
[cols="<2,<8"]
|
[cols="<2,<8"]
|
[grid="topbot"]
|
[grid="topbot"]
|
|=======================
|
|=======================
|
| Hardware version: | `1.4.9.8`
|
| Hardware version: | `1.4.9.8`
|
