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in the root directory of the NEORV32 repository. Please also check out the <<_legal>> section.
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in the root directory of the NEORV32 repository. Please also check out the <<_legal>> section.
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**Structure**
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**Structure**
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* <<_neorv32_processor_soc>>
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[start=1]
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* <<_neorv32_central_processing_unit_cpu>>
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. <<_neorv32_processor_soc>>
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* <<_on_chip_debugger_ocd>>
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. <<_neorv32_central_processing_unit_cpu>>
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* <<_software_framework>>
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. <<_on_chip_debugger_ocd>>
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. <<_software_framework>>
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[TIP]
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[TIP]
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Links in this document are <<_overview,highlighted>>.
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Links in this document are <<_overview,highlighted>>.
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│├references - Data sheets and RISC-V specs.
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│├references - Data sheets and RISC-V specs.
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│└src_adoc - AsciiDoc sources for this document
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│└src_adoc - AsciiDoc sources for this document
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│
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│
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├rtl - VHDL sources
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├rtl - VHDL sources
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│├core - Core sources of the CPU & SoC
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│├core - Core sources of the CPU & SoC
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││└mem - SoC-internal memories (default architectures)
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│├processor_templates - Pre-configured SoC wrappers
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│├processor_templates - Pre-configured SoC wrappers
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│├system_integration - System wrappers for advanced connectivity
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│├system_integration - System wrappers for advanced connectivity
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│└test_setups - Minimal test setup "SoCs" used in the User Guide
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│└test_setups - Minimal test setup "SoCs" used in the User Guide
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│
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│
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├setups - Example setups for various FPGAs, boards and toolchains
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├setups - Example setups for various FPGAs, boards and toolchains
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├neorv32_busswitch.vhd - Processor bus switch for CPU buses (I&D)
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├neorv32_busswitch.vhd - Processor bus switch for CPU buses (I&D)
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├neorv32_bus_keeper.vhd - Processor-internal bus monitor
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├neorv32_bus_keeper.vhd - Processor-internal bus monitor
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├neorv32_cfs.vhd - Custom functions subsystem
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├neorv32_cfs.vhd - Custom functions subsystem
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├neorv32_debug_dm.vhd - on-chip debugger: debug module
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├neorv32_debug_dm.vhd - on-chip debugger: debug module
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├neorv32_debug_dtm.vhd - on-chip debugger: debug transfer module
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├neorv32_debug_dtm.vhd - on-chip debugger: debug transfer module
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├neorv32_dmem.vhd - Processor-internal data memory
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├neorv32_dmem.entity.vhd - Processor-internal data memory (entity-only!)
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├neorv32_gpio.vhd - General purpose input/output port unit
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├neorv32_gpio.vhd - General purpose input/output port unit
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├neorv32_icache.vhd - Processor-internal instruction cache
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├neorv32_icache.vhd - Processor-internal instruction cache
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├neorv32_imem.vhd - Processor-internal instruction memory
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├neorv32_imem.entity.vhd - Processor-internal instruction memory (entity-only!)
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│└neor32_application_image.vhd - IMEM application initialization image
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│└neor32_application_image.vhd - IMEM application initialization image
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├neorv32_mtime.vhd - Machine system timer
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├neorv32_mtime.vhd - Machine system timer
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├neorv32_neoled.vhd - NeoPixel (TM) compatible smart LED interface
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├neorv32_neoled.vhd - NeoPixel (TM) compatible smart LED interface
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├neorv32_pwm.vhd - Pulse-width modulation controller
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├neorv32_pwm.vhd - Pulse-width modulation controller
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├neorv32_spi.vhd - Serial peripheral interface controller
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├neorv32_spi.vhd - Serial peripheral interface controller
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├neorv32_trng.vhd - True random number generator
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├neorv32_trng.vhd - True random number generator
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├neorv32_twi.vhd - Two wire serial interface controller
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├neorv32_twi.vhd - Two wire serial interface controller
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├neorv32_uart.vhd - Universal async. receiver/transmitter
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├neorv32_uart.vhd - Universal async. receiver/transmitter
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├neorv32_wdt.vhd - Watchdog timer
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├neorv32_wdt.vhd - Watchdog timer
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├neorv32_wishbone.vhd - External (Wishbone) bus interface
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├neorv32_wishbone.vhd - External (Wishbone) bus interface
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└neorv32_xirq.vhd - External interrupt controller
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│
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├mem/neorv32_dmem.default.vhd - _Default_ data memory (architecture-only!)
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└mem/neorv32_imem.default.vhd - _Default_ instruction memory (architecture-only!)
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...................................
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...................................
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[NOTE]
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The processor-internal instruction and data memories (IMEM and DMEM) are split into two design files each:
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a plain entity definition (`neorv32_*mem.entity.vhd`) and the actual architecture definition
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(`mem/neorv32_*mem.default.vhd`). The **default** architecture definitions from `rtl/core/mem` provide a _generic_ and
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_platform independent_ memory design that (should) infers embedded memory blocks. You can replace/modify the architecture
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source file in order to use platform-specific features (like advanced memory resources) or to improve technology mapping
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and/or timing.
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// ####################################################################################################################
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// ####################################################################################################################
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:sectnums:
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:sectnums:
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=== FPGA Implementation Results
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=== FPGA Implementation Results
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