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of the CoreMark MCU benchmark and the official RISC-V architecture test suite. RISC-V GCC is used as
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of the CoreMark MCU benchmark and the official RISC-V architecture test suite. RISC-V GCC is used as
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default toolchain (https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt toolchains are also provided]).
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default toolchain (https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt toolchains are also provided]).
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[TIP]
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[TIP]
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Check out the processor's **https://stnolting.github.io/neorv32/ug[online User Guide]**
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Check out the processor's **https://stnolting.github.io/neorv32/ug[online User Guide]**
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that provides hands-on tutorial to get you started.
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that provides hands-on tutorials to get you started.
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[TIP]
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The project's change log is available in https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md[CHANGELOG.md]
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The project's change log is available in https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md[CHANGELOG.md]
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in the root directory of the NEORV32 repository. Please also check out the <<_legal>> section.
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in the root directory of the NEORV32 repository. Please also check out the <<_legal>> section.
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**Structure**
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**Structure**
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. <<_neorv32_processor_soc>>
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. <<_neorv32_processor_soc>>
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. <<_neorv32_central_processing_unit_cpu>>
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. <<_neorv32_central_processing_unit_cpu>>
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. <<_software_framework>>
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. <<_software_framework>>
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. <<_on_chip_debugger_ocd>>
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. <<_on_chip_debugger_ocd>>
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[TIP]
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Links in this document are <<_overview,highlighted>>.
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// ####################################################################################################################
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// ####################################################################################################################
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:sectnums:
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:sectnums:
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** optional serial interfaces (UARTs, TWI, SPI)
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** optional serial interfaces (UARTs, TWI, SPI)
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** optional timers and counters (WDT, MTIME)
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** optional timers and counters (WDT, MTIME)
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** optional general purpose IO and PWM and native NeoPixel (c) compatible smart LED interface
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** optional general purpose IO and PWM and native NeoPixel (c) compatible smart LED interface
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** optional embedded memories / caches for data, instructions and bootloader
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** optional embedded memories / caches for data, instructions and bootloader
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** optional external memory interface (Wishbone / AXI4-Lite) and stream link interface (AXI4-Stream) for custom connectivity
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** optional external memory interface (Wishbone / AXI4-Lite) and stream link interface (AXI4-Stream) for custom connectivity
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** optional execute in place (XIP) module
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** on-chip debugger compatible with OpenOCD and gdb
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** on-chip debugger compatible with OpenOCD and gdb
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* **Software framework**
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* **Software framework**
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** GCC-based toolchain - prebuilt toolchains available; application compilation based on GNU makefiles
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** GCC-based toolchain - prebuilt toolchains available; application compilation based on GNU makefiles
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** internal bootloader with serial user interface
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** internal bootloader with serial user interface
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** core libraries for high-level usage of the provided functions and peripherals
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** core libraries for high-level usage of the provided functions and peripherals
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├neorv32_trng.vhd - True random number generator
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├neorv32_trng.vhd - True random number generator
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├neorv32_twi.vhd - Two wire serial interface controller
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├neorv32_twi.vhd - Two wire serial interface controller
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├neorv32_uart.vhd - Universal async. receiver/transmitter
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├neorv32_uart.vhd - Universal async. receiver/transmitter
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├neorv32_wdt.vhd - Watchdog timer
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├neorv32_wdt.vhd - Watchdog timer
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├neorv32_wishbone.vhd - External (Wishbone) bus interface
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├neorv32_wishbone.vhd - External (Wishbone) bus interface
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├neorv32_xip.vhd - Execute in place module
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├neorv32_xirq.vhd - External interrupt controller
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├neorv32_xirq.vhd - External interrupt controller
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│
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│
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├mem/neorv32_dmem.default.vhd - _Default_ data memory (architecture-only)
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├mem/neorv32_dmem.default.vhd - _Default_ data memory (architecture-only)
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└mem/neorv32_imem.default.vhd - _Default_ instruction memory (architecture-only)
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└mem/neorv32_imem.default.vhd - _Default_ instruction memory (architecture-only)
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...................................
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...................................
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==== CPU
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==== CPU
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[cols="<2,<8"]
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[cols="<2,<8"]
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[grid="topbot"]
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[grid="topbot"]
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|=======================
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|=======================
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| Hardware version: | `1.5.7.10`
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| Top entity: | `rtl/core/neorv32_cpu.vhd`
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| Top entity: | `rtl/core/neorv32_cpu.vhd`
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| FPGA: | Intel Cyclone IV E `EP4CE22F17C6`
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| FPGA: | Intel Cyclone IV E `EP4CE22F17C6`
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| Toolchain: | Quartus Prime 20.1.0
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| Toolchain: | Quartus Prime 20.1.0
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|=======================
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|=======================
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==== Processor Modules
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==== Processor Modules
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[cols="<2,<8"]
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[cols="<2,<8"]
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[grid="topbot"]
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[grid="topbot"]
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|=======================
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|=======================
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| Hardware version: | `1.5.7.15`
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| Top entity: | `rtl/core/neorv32_top.vhd`
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| Top entity: | `rtl/core/neorv32_top.vhd`
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| FPGA: | Intel Cyclone IV E `EP4CE22F17C6`
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| FPGA: | Intel Cyclone IV E `EP4CE22F17C6`
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| Toolchain: | Quartus Prime 20.1.0
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| Toolchain: | Quartus Prime 20.1.0
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|=======================
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|=======================
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
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| Module | Description | LEs | FFs | MEM bits | DSPs
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| Module | Description | LEs | FFs | MEM bits | DSPs
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| Boot ROM | Bootloader ROM (4kB) | 2 | 1 | 32768 | 0
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| Boot ROM | Bootloader ROM (4kB) | 2 | 1 | 32768 | 0
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| **BUSKEEPER** | Processor-internal bus monitor | 9 | 6 | 0 | 0
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| **BUSKEEPER** | Processor-internal bus monitor | 9 | 6 | 0 | 0
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| **BUSSWITCH** | Bus mux for CPU instr. and data interface | 63 | 8 | 0 | 0
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| **BUSSWITCH** | Bus multiplexer for CPU instr. and data interface | 63 | 8 | 0 | 0
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| CFS | Custom functions subsystemfootnote:[Resource utilization depends on actually implemented custom functionality.] | - | - | - | -
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| CFS | Custom functions subsystemfootnote:[Resource utilization depends on actually implemented custom functionality.] | - | - | - | -
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| DMEM | Processor-internal data memory (8kB) | 19 | 2 | 65536 | 0
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| DMEM | Processor-internal data memory (8kB) | 19 | 2 | 65536 | 0
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| DM | On-chip debugger - debug module | 493 | 240 | 0 | 0
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| DM | On-chip debugger - debug module | 493 | 240 | 0 | 0
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| DTM | On-chip debugger - debug transfer module (JTAG) | 254 | 218 | 0 | 0
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| DTM | On-chip debugger - debug transfer module (JTAG) | 254 | 218 | 0 | 0
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| GPIO | General purpose input/output ports | 134 | 161 | 0 | 0
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| GPIO | General purpose input/output ports | 134 | 161 | 0 | 0
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| Line 342... |
Line 337... |
| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 183 | 132 | 0 | 0
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| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 183 | 132 | 0 | 0
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| WDT | Watchdog timer | 53 | 43 | 0 | 0
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| WDT | Watchdog timer | 53 | 43 | 0 | 0
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| WISHBONE | External memory interface | 114 | 110 | 0 | 0
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| WISHBONE | External memory interface | 114 | 110 | 0 | 0
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| XIRQ | External interrupt controller (32 channels) | 241 | 201 | 0 | 0
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| XIRQ | External interrupt controller (32 channels) | 241 | 201 | 0 | 0
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| GPTMR | General Purpose Timer | 153 | 107 | 0 | 0
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| GPTMR | General Purpose Timer | 153 | 107 | 0 | 0
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| XIP | Execute in place module | 305 | 243 | 0 | 0
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|=======================
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|=======================
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:sectnums:
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:sectnums:
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