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default toolchain (https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt toolchains are also provided]).
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default toolchain (https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt toolchains are also provided]).
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[TIP]
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[TIP]
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Check out the processor's **https://stnolting.github.io/neorv32/ug[online User Guide]**
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Check out the processor's **https://stnolting.github.io/neorv32/ug[online User Guide]**
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that provides hands-on tutorials to get you started.
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that provides hands-on tutorials to get you started.
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The project's change log is available in https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md[CHANGELOG.md]
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The project's change log is available in https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md[CHANGELOG.md]
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in the root directory of the NEORV32 repository. Please also check out the <<_legal>> section.
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in the root directory of the NEORV32 repository. Please also check out the <<_legal>> section.
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**Structure**
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**Structure**
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* fully synchronous design, no latches, no gated clocks
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* fully synchronous design, no latches, no gated clocks
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* small hardware footprint and high operating frequency for easy integration
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* small hardware footprint and high operating frequency for easy integration
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* **NEORV32 CPU**: 32-bit `rv32i` RISC-V CPU
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* **NEORV32 CPU**: 32-bit `rv32i` RISC-V CPU
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** RISC-V compatibility: passes the official architecture tests
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** RISC-V compatibility: passes the official architecture tests
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** base architecture + privileged architecture (optional) + ISA extensions (optional)
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** base architecture + privileged architecture (optional) + ISA extensions (optional)
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** option to add custom RISC-V instructions (as custom ISA extension)
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** rich set of customization options (ISA extensions, design goal: performance / area (/ energy), ...)
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** rich set of customization options (ISA extensions, design goal: performance / area (/ energy), ...)
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** aims to support <<_full_virtualization>> capabilities (CPU _and_ SoC) to increase execution safety
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** aims to support <<_full_virtualization>> capabilities (CPU _and_ SoC) to increase execution safety
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** official https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md[RISC-V open source architecture ID]
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** official https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md[RISC-V open source architecture ID]
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* **NEORV32 Processor (SoC)**: highly-configurable full-scale microcontroller-like processor system
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* **NEORV32 Processor (SoC)**: highly-configurable full-scale microcontroller-like processor system
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** based on the NEORV32 CPU
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** based on the NEORV32 CPU
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** optional timers and counters (WDT, MTIME)
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** optional timers and counters (WDT, MTIME)
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** optional general purpose IO and PWM and native NeoPixel (c) compatible smart LED interface
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** optional general purpose IO and PWM and native NeoPixel (c) compatible smart LED interface
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** optional embedded memories / caches for data, instructions and bootloader
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** optional embedded memories / caches for data, instructions and bootloader
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** optional external memory interface (Wishbone / AXI4-Lite) and stream link interface (AXI4-Stream) for custom connectivity
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** optional external memory interface (Wishbone / AXI4-Lite) and stream link interface (AXI4-Stream) for custom connectivity
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** optional execute in place (XIP) module
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** optional execute in place (XIP) module
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** on-chip debugger compatible with OpenOCD and gdb
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** on-chip debugger compatible with OpenOCD and gdb including hardware trigger module
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* **Software framework**
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* **Software framework**
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** GCC-based toolchain - prebuilt toolchains available; application compilation based on GNU makefiles
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** GCC-based toolchain - prebuilt toolchains available; application compilation based on GNU makefiles
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** internal bootloader with serial user interface
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** internal bootloader with serial user interface
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** core libraries for high-level usage of the provided functions and peripherals
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** core libraries for high-level usage of the provided functions and peripherals
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** runtime environment and several example programs
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** runtime environment and several example programs
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[TIP]
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[TIP]
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For more in-depth details regarding the feature provided by he hardware see the according sections:
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For more in-depth details regarding the feature provided by he hardware see the according sections:
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<<_neorv32_central_processing_unit_cpu>> and <<_neorv32_processor_soc>>.
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<<_neorv32_central_processing_unit_cpu>> and <<_neorv32_processor_soc>>.
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**Extensibility and Customization**
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The NEORV32 processor was designed to ease customization and extensibility and provides several options for adding
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application-specific custom hardware modules and accelerators. The three most common options for adding custom
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on-chip modules are listed below.
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* <<_processor_external_memory_interface_wishbone_axi4_lite>> for processor-external modules
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* <<_custom_functions_subsystem_cfs>> for tightly-coupled processor-internal co-processors
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* <<_custom_functions_unit_cfu>> for custom RISC-V instructions
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[TIP]
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A more detailed comparison of the extension/customization options can be found in section
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https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules[Adding Custom Hardware Modules]
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of the user guide.
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// ####################################################################################################################
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// ####################################################################################################################
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:sectnums:
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:sectnums:
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=== Project Folder Structure
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=== Project Folder Structure
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├neorv32_package.vhd - Processor/CPU main VHDL package file
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├neorv32_package.vhd - Processor/CPU main VHDL package file
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│
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│
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├neorv32_cpu.vhd - NEORV32 CPU top entity
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├neorv32_cpu.vhd - NEORV32 CPU top entity
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│├neorv32_cpu_alu.vhd - Arithmetic/logic unit
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│├neorv32_cpu_alu.vhd - Arithmetic/logic unit
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││├neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor (B ext.)
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││├neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor (B ext.)
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││├neorv32_cpu_cp_cfu.vhd - Custom functions (instruction) co-processor (Zxcfu ext.)
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││├neorv32_cpu_cp_fpu.vhd - Floating-point co-processor (Zfinx ext.)
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││├neorv32_cpu_cp_fpu.vhd - Floating-point co-processor (Zfinx ext.)
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││├neorv32_cpu_cp_muldiv.vhd - Mul/Div co-processor (M extension)
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││├neorv32_cpu_cp_muldiv.vhd - Mul/Div co-processor (M extension)
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││└neorv32_cpu_cp_shifter.vhd - Bit-shift co-processor
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││└neorv32_cpu_cp_shifter.vhd - Bit-shift co-processor
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│├neorv32_cpu_bus.vhd - Bus interface + physical memory protection
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│├neorv32_cpu_bus.vhd - Bus interface + physical memory protection
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│├neorv32_cpu_control.vhd - CPU control, exception/IRQ system and CSRs
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│├neorv32_cpu_control.vhd - CPU control, exception/IRQ system and CSRs
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