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The software framework of the processor comes with application makefiles, software libraries for all CPU
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The software framework of the processor comes with application makefiles, software libraries for all CPU
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and processor features, a bootloader, a runtime environment and several example programs - including a port
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and processor features, a bootloader, a runtime environment and several example programs - including a port
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of the CoreMark MCU benchmark and the official RISC-V architecture test suite. RISC-V GCC is used as
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of the CoreMark MCU benchmark and the official RISC-V architecture test suite. RISC-V GCC is used as
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default toolchain (https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt toolchains are also provided]).
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default toolchain (https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt toolchains are also provided]).
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[TIP]
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Check out the processor's **https://stnolting.github.io/neorv32/ug[online User Guide]**
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Check out the processor's **https://stnolting.github.io/neorv32/ug[online User Guide]**
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that provides hands-on tutorials to get you started.
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that provides hands-on tutorials to get you started.
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The project's change log is available in https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md[CHANGELOG.md]
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in the root directory of the NEORV32 repository. Please also check out the <<_legal>> section.
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**Structure**
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**Structure**
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[start=2]
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[start=2]
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. <<_neorv32_processor_soc>>
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. <<_neorv32_processor_soc>>
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. <<_neorv32_central_processing_unit_cpu>>
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. <<_neorv32_central_processing_unit_cpu>>
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. <<_software_framework>>
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. <<_software_framework>>
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. <<_on_chip_debugger_ocd>>
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. <<_on_chip_debugger_ocd>>
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. <<_legal>>
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**Annotations**
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[WARNING]
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Warning
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[IMPORTANT]
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Important
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[NOTE]
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Note
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[TIP]
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Tip
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// ####################################################################################################################
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// ####################################################################################################################
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Line 223... |
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// ####################################################################################################################
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// ####################################################################################################################
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:sectnums:
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:sectnums:
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=== FPGA Implementation Results
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=== FPGA Implementation Results
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This chapter shows _exemplary_ implementation results of the NEORV32 CPU and NEORV32 Processor.
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This section shows _exemplary_ FPGA implementation results for the NEORV32 CPU and NEORV32 Processor modules.
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Note that certain configuration options might also have an impact on other configuration options. Furthermore,
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this report cannot cover all possible option combinations. Hence, the presented implementation results are
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just _exemplary_. If not otherwise mentioned all implementations use the default generic configurations.
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:sectnums:
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:sectnums:
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==== CPU
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==== CPU
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[cols="<2,<8"]
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[cols="<2,<8"]
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[grid="topbot"]
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[grid="topbot"]
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|=======================
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|=======================
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| HW version: | `1.6.8.3`
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| Top entity: | `rtl/core/neorv32_cpu.vhd`
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| Top entity: | `rtl/core/neorv32_cpu.vhd`
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| FPGA: | Intel Cyclone IV E `EP4CE22F17C6`
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| FPGA: | Intel Cyclone IV E `EP4CE22F17C6`
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| Toolchain: | Quartus Prime 20.1.0
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| Toolchain: | Quartus Prime Lite 21.1
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| Constraints: | **no timing constraints**, "_balanced optimization_", f~max~ from "_Slow 1200mV 0C Model_"
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|=======================
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|=======================
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[cols="<5,>1,>1,>1,>1,>1"]
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[cols="<6,>1,>1,>1,>1,>1"]
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
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| CPU | LEs | FFs | MEM bits | DSPs | _f~max~_
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| CPU ISA Configuration | LEs | FFs | MEM bits | DSPs | _f~max~_
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| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz
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| `rv32e` | 900 | 388 | 512 | 0 | 121 MHz
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| `rv32i_Zicsr_Zicntr` | 1729 | 813 | 1024 | 0 | 124 MHz
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| `rv32i` | 904 | 388 | 1024 | 0 | 121 MHz
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| `rv32im_Zicsr_Zicntr` | 2269 | 1055 | 1024 | 0 | 124 MHz
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| `rv32i_Zicsr` | 1425 | 673 | 1024 | 0 | 118 MHz
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| `rv32imc_Zicsr_Zicntr` | 2501 | 1070 | 1024 | 0 | 124 MHz
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| `rv32i_Zicsr_Zicntr` | 1778 | 803 | 1024 | 0 | 118 MHz
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| `rv32imac_Zicsr_Zicntr` | 2511 | 1074 | 1024 | 0 | 124 MHz
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| `rv32im_Zicsr_Zicntr` | 2244 | 978 | 1024 | 0 | 118 MHz
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| `rv32imacu_Zicsr_Zicntr` | 2521 | 1079 | 1024 | 0 | 124 MHz
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| `rv32ima_Zicsr_Zicntr` | 2267 | 982 | 1024 | 0 | 118 MHz
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| `rv32imacu_Zicsr_Zicntr_Zifencei` | 2522 | 1079 | 1024 | 0 | 122 MHz
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| `rv32imac_Zicsr_Zicntr` | 2453 | 994 | 1024 | 0 | 118 MHz
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| `rv32imacu_Zicsr_Zicntr_Zifencei_Zfinx` | 3807 | 1731 | 1024 | 7 | 116 MHz
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| `rv32imacb_Zicsr_Zicntr` | 3270 | 1249 | 1024 | 0 | 118 MHz
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| `rv32imacu_Zicsr_Zicntr_Zifencei_Zfinx_DebugMode` | 3974 | 1815 | 1024 | 7 | 116 MHz
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| `rv32imacbu_Zicsr_Zicntr` | 3286 | 1254 | 1024 | 0 | 118 MHz
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| `rv32imacbu_Zicsr_Zicntr_Zifencei` | 3278 | 1254 | 1024 | 0 | 118 MHz
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| `rv32imacbu_Zicsr_Zicntr_Zifencei_Zfinx` | 4536 | 1906 | 1024 | 7 | 115 MHz
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| `rv32imacbu_Zicsr_Zicntr_Zifencei_Zfinx_DebugMode` | 5989 | 2416 | 1024 | 7 | 110 MHz
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|=======================
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|=======================
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.**RISC-V Compliance**
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[NOTE]
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The `Zicsr` ISA extension implements the privileged machine architecture
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(see <<_zicsr_control_and_status_register_access_privileged_architecture>>). The `Zicntr` ISA
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extension implements the basic counters and timers (see <<_zicntr_cpu_base_counters>>). Both
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extensions are _mandatory_ in order to comply with the RISC-V architecture specifications.
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[NOTE]
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The table above does not show _all_ CPU ISA extensions. More sophisticated and application-specific
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options like PMP and HMP are not included in this overview.
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.Goal-Driven Optimization
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[TIP]
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[TIP]
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The CPU provides further options to reduce the area footprint (for example by constraining the CPU-internal
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The CPU provides further options to reduce the area footprint (for example by constraining the CPU-internal
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counter sizes) or to increase performance (for example by using a barrel-shifter; at cost of extra hardware).
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counter sizes) or to increase performance (for example by using a barrel-shifter; at cost of extra hardware).
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See section <<_processor_top_entity_generics>> for more information. Also, take a look at the User Guide section
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See section <<_processor_top_entity_generics>> for more information. Also, take a look at the User Guide section
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https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration].
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https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration].
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:sectnums:
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:sectnums:
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==== Processor Modules
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==== Processor - Modules
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[cols="<2,<8"]
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[cols="<2,<8"]
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[grid="topbot"]
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[grid="topbot"]
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|=======================
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|=======================
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| HW version: | `1.6.8.3`
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| Top entity: | `rtl/core/neorv32_top.vhd`
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| Top entity: | `rtl/core/neorv32_top.vhd`
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| FPGA: | Intel Cyclone IV E `EP4CE22F17C6`
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| FPGA: | Intel Cyclone IV E `EP4CE22F17C6`
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| Toolchain: | Quartus Prime 20.1.0
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| Toolchain: | Quartus Prime Lite 21.1
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| Constraints: | **no timing constraints**, "_balanced optimization_"
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|=======================
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|=======================
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|
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.Hardware utilization by the processor modules (mandatory core modules in **bold**)
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.Hardware utilization by processor module (mandatory modules highlighted in **bold**)
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[cols="<2,<8,>1,>1,>2,>1"]
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[cols="<2,<8,>1,>1,>2,>1"]
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
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| Module | Description | LEs | FFs | MEM bits | DSPs
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| Module | Description | LEs | FFs | MEM bits | DSPs
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| Boot ROM | Bootloader ROM (4kB) | 2 | 1 | 32768 | 0
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| Boot ROM | Bootloader ROM (4kB) | 3 | 2 | 32768 | 0
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| **BUSKEEPER** | Processor-internal bus monitor | 9 | 6 | 0 | 0
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| **BUSKEEPER** | Processor-internal bus monitor | 28 | 15 | 0 | 0
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| **BUSSWITCH** | Bus multiplexer for CPU instr. and data interface | 63 | 8 | 0 | 0
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| **BUSSWITCH** | Bus multiplexer for CPU instr. and data interface | 69 | 8 | 0 | 0
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| CFS | Custom functions subsystemfootnote:[Resource utilization depends on actually implemented custom functionality.] | - | - | - | -
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| CFS | Custom functions subsystemfootnote:[Resource utilization depends on custom design logic.] | - | - | - | -
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| DMEM | Processor-internal data memory (8kB) | 19 | 2 | 65536 | 0
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| DM | On-chip debugger - debug module | 473 | 240 | 0 | 0
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| DM | On-chip debugger - debug module | 493 | 240 | 0 | 0
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| DTM | On-chip debugger - debug transfer module (JTAG) | 259 | 221 | 0 | 0
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| DTM | On-chip debugger - debug transfer module (JTAG) | 254 | 218 | 0 | 0
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| DMEM | Processor-internal data memory (8kB) | 18 | 2 | 65536 | 0
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| GPIO | General purpose input/output ports | 134 | 161 | 0 | 0
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| GPIO | General purpose input/output ports | 102 | 98 | 0 | 0
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| iCACHE | Instruction cache (1x4 blocks, 256 bytes per block) | 2 21| 156 | 8192 | 0
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| GPTMR | General Purpose Timer | 153 | 105 | 0 | 0
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| IMEM | Processor-internal instruction memory (16kB) | 13 | 2 | 131072 | 0
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| iCACHE | Instruction cache (2x4 blocks, 64 bytes per block) | 417 | 297 | 4096 | 0
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| MTIME | Machine system timer | 319 | 167 | 0 | 0
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| IMEM | Processor-internal instruction memory (16kB) | 12 | 2 | 131072 | 0
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| NEOLED | Smart LED Interface (NeoPixel/WS28128) [FIFO_depth=1] | 226 | 182 | 0 | 0
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| MTIME | Machine system timer | 345 | 166 | 0 | 0
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| SLINK | Stream link interface (2xRX, 2xTX, FIFO_depth=1) | 208 | 181 | 0 | 0
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| NEOLED | Smart LED Interface (NeoPixel/WS28128) (FIFO_depth=1) | 227 | 184 | 0 | 0
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| PWM | Pulse_width modulation controller (4 channels) | 71 | 69 | 0 | 0
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| PWM | Pulse_width modulation controller (8 channels) | 128 | qq7 | 0 | 0
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| SPI | Serial peripheral interface | 148 | 127 | 0 | 0
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| SLINK | Stream link interface (2xRX, 2xTX, FIFO_depth=1) | 136 | 116 | 0 | 0
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| **SYSINFO** | System configuration information memory | 14 | 11 | 0 | 0
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| SPI | Serial peripheral interface | 114 | 94 | 0 | 0
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| TRNG | True random number generator | 89 | 76 | 0 | 0
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| **SYSINFO** | System configuration information memory | 13 | 11 | 0 | 0
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| TRNG | True random number generator | 89 | 79 | 0 | 0
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| TWI | Two-wire interface | 77 | 43 | 0 | 0
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| TWI | Two-wire interface | 77 | 43 | 0 | 0
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| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 183 | 132 | 0 | 0
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| UART0, UART1 | Universal asynchronous receiver/transmitter 0/1 (FIFO_depth=1) | 195 | 143 | 0 | 0
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| WDT | Watchdog timer | 53 | 43 | 0 | 0
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| WDT | Watchdog timer | 61 | 46 | 0 | 0
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| WISHBONE | External memory interface | 114 | 110 | 0 | 0
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| WISHBONE | External memory interface | 120 | 112 | 0 | 0
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| XIRQ | External interrupt controller (32 channels) | 241 | 201 | 0 | 0
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| XIP | Execute in place module | 318 | 244 | 0 | 0
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| GPTMR | General Purpose Timer | 153 | 107 | 0 | 0
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| XIRQ | External interrupt controller (32 channels) | 245 | 200 | 0 | 0
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| XIP | Execute in place module | 305 | 243 | 0 | 0
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|=======================
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|=======================
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|
|
|
[NOTE]
|
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Note that not all IOs were actually connected to FPGA pins (for example some GPIO inputs and outputs)
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when generating these reports.
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:sectnums:
|
:sectnums:
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==== Exemplary Setups
|
==== Exemplary Setups
|
|
|
| Line 335... |
Line 373... |
| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04**
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| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04**
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| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34**
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| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34**
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| _performance_ (`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54**
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| _performance_ (`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54**
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|=======================
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|=======================
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|
|
[IMPORTANT]
|
[NOTE]
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The CoreMark results were generated using a `rv32i` toolchain. This toolchain supports standard extensions
|
The CoreMark results were generated using a `rv32i` toolchain. This toolchain supports standard extensions
|
like `M` and `C` but the built-in libraries only use the base `I` ISA.
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like `M` and `C` but the built-in libraries only use the base `I` ISA.
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|
|
[NOTE]
|
[NOTE]
|
The "_performance_" CPU configuration uses the <<_fast_mul_en>> and <<_fast_shift_en>> options.
|
The "_performance_" CPU configuration uses the <<_fast_mul_en>> and <<_fast_shift_en>> options.
|
|
|
[NOTE]
|
|
The NEORV32 CPU is based on a multi-cycle architecture. Each instruction is executed in a sequence of
|
The NEORV32 CPU is based on a multi-cycle architecture. Each instruction is executed in a sequence of
|
several consecutive micro operations.
|
several consecutive micro operations.
|
|
|
[NOTE]
|
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on
|
the available CPU extensions. The average CPI is computed by dividing the total number of required clock cycles
|
the available CPU extensions. The average CPI is computed by dividing the total number of required clock cycles
|
(only the timed core to avoid distortion due to IO wait cycles) by the number of executed instructions
|
(only the timed core to avoid distortion due to IO wait cycles) by the number of executed instructions
|
(`[m]instret[h]` CSRs).
|
(`[m]instret[h]` CSRs). More information regarding the execution time of each implemented instruction can be found in
|
|
|
[TIP]
|
|
More information regarding the execution time of each implemented instruction can be found in
|
|
chapter <<_instruction_timing>>.
|
chapter <<_instruction_timing>>.
|
