| Line 137... |
Line 137... |
├example - Various example programs
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├example - Various example programs
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│└...
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│└...
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├lib - Processor core library
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├lib - Processor core library
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│├include - Header files (*.h)
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│├include - Header files (*.h)
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│└source - Source files (*.c)
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│└source - Source files (*.c)
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├image_gen - Helper program to generate NEORV32 executables
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├image_gen - Helper program to generate NEORV32 executables^
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├isa-test
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│├riscv-arch-test - RISC-V spec. compatibility test framework (submodule)
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│└port-neorv32 - Port files for the official RISC-V architecture tests
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├ocd_firmware - Source code for on-chip debugger's "park loop"
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├ocd_firmware - Source code for on-chip debugger's "park loop"
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├openocd - OpenOCD on-chip debugger configuration files
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├openocd - OpenOCD on-chip debugger configuration files
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└svd - Processor system view description file (CMSIS-SVD)
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└svd - Processor system view description file (CMSIS-SVD)
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...................................
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...................................
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| Line 234... |
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==== CPU
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==== CPU
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|
|
[cols="<2,<8"]
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[cols="<2,<8"]
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[grid="topbot"]
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[grid="topbot"]
|
|=======================
|
|=======================
|
| HW version: | `1.6.8.3`
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| HW version: | `1.6.9.8`
|
| Top entity: | `rtl/core/neorv32_cpu.vhd`
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| Top entity: | `rtl/core/neorv32_cpu.vhd`
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| FPGA: | Intel Cyclone IV E `EP4CE22F17C6`
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| FPGA: | Intel Cyclone IV E `EP4CE22F17C6`
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| Toolchain: | Quartus Prime Lite 21.1
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| Toolchain: | Quartus Prime Lite 21.1
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| Constraints: | **no timing constraints**, "_balanced optimization_", f~max~ from "_Slow 1200mV 0C Model_"
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| Constraints: | **no timing constraints**, "_balanced optimization_", f~max~ from "_Slow 1200mV 0C Model_"
|
|=======================
|
|=======================
|
|
|
[cols="<6,>1,>1,>1,>1,>1"]
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[cols="<6,>1,>1,>1,>1,>1"]
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
|
|=======================
|
| CPU ISA Configuration | LEs | FFs | MEM bits | DSPs | _f~max~_
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| CPU ISA Configuration | LEs | FFs | MEM bits | DSPs | _f~max~_
|
| `rv32e` | 900 | 388 | 512 | 0 | 121 MHz
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| `rv32e` | 830 | 400 | 512 | 0 | 129 MHz
|
| `rv32i` | 904 | 388 | 1024 | 0 | 121 MHz
|
| `rv32i` | 834 | 400 | 1024 | 0 | 129 MHz
|
| `rv32i_Zicsr` | 1425 | 673 | 1024 | 0 | 118 MHz
|
| `rv32i_Zicsr` | 1328 | 678 | 1024 | 0 | 128 MHz
|
| `rv32i_Zicsr_Zicntr` | 1778 | 803 | 1024 | 0 | 118 MHz
|
| `rv32i_Zicsr_Zicntr` | 1614 | 808 | 1024 | 0 | 128 MHz
|
| `rv32im_Zicsr_Zicntr` | 2244 | 978 | 1024 | 0 | 118 MHz
|
| `rv32im_Zicsr_Zicntr` | 2087 | 983 | 1024 | 0 | 128 MHz
|
| `rv32ima_Zicsr_Zicntr` | 2267 | 982 | 1024 | 0 | 118 MHz
|
| `rv32ima_Zicsr_Zicntr` | 2129 | 987 | 1024 | 0 | 128 MHz
|
| `rv32imac_Zicsr_Zicntr` | 2453 | 994 | 1024 | 0 | 118 MHz
|
| `rv32imac_Zicsr_Zicntr` | 2338 | 992 | 1024 | 0 | 128 MHz
|
| `rv32imacb_Zicsr_Zicntr` | 3270 | 1249 | 1024 | 0 | 118 MHz
|
| `rv32imacb_Zicsr_Zicntr` | 3175 | 1247 | 1024 | 0 | 128 MHz
|
| `rv32imacbu_Zicsr_Zicntr` | 3286 | 1254 | 1024 | 0 | 118 MHz
|
| `rv32imacbu_Zicsr_Zicntr` | 3186 | 1254 | 1024 | 0 | 128 MHz
|
| `rv32imacbu_Zicsr_Zicntr_Zifencei` | 3278 | 1254 | 1024 | 0 | 118 MHz
|
| `rv32imacbu_Zicsr_Zicntr_Zifencei` | 3187 | 1254 | 1024 | 0 | 128 MHz
|
| `rv32imacbu_Zicsr_Zicntr_Zifencei_Zfinx` | 4536 | 1906 | 1024 | 7 | 115 MHz
|
| `rv32imacbu_Zicsr_Zicntr_Zifencei_Zfinx` | 4450 | 1906 | 1024 | 7 | 123 MHz
|
| `rv32imacbu_Zicsr_Zicntr_Zifencei_Zfinx_DebugMode` | 5989 | 2416 | 1024 | 7 | 110 MHz
|
| `rv32imacbu_Zicsr_Zicntr_Zifencei_Zfinx_DebugMode` | 4825 | 2018 | 1024 | 7 | 123 MHz
|
|=======================
|
|=======================
|
|
|
.**RISC-V Compliance**
|
.**RISC-V Compliance**
|
[NOTE]
|
[NOTE]
|
The `Zicsr` ISA extension implements the privileged machine architecture
|
The `Zicsr` ISA extension implements the privileged machine architecture
|
