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co-processors and even user-defined instructions.
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co-processors and even user-defined instructions.
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**Why RISC-V?**
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**Why RISC-V?**
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image::riscv_logo.png[width=250,align=left]
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[quote, RISC-V International, https://riscv.org/about/]
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[quote, RISC-V International, https://riscv.org/about/]
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____
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____
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RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.
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RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.
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____
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____
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just beat existing ones like https://github.com/SpinalHDL/VexRiscv[VexRISC] in terms of performance or
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just beat existing ones like https://github.com/SpinalHDL/VexRiscv[VexRISC] in terms of performance or
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https://github.com/olofk/serv[SERV] in terms of size. It was build having a different design goal in mind.
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https://github.com/olofk/serv[SERV] in terms of size. It was build having a different design goal in mind.
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The project aims to provide _another option_ in the RISC-V / soft-core design space with a different performance
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The project aims to provide _another option_ in the RISC-V / soft-core design space with a different performance
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vs. size trade-off and a different focus: _embrace_ concepts like documentation, platform-independence / portability,
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vs. size trade-off and a different focus: _embrace_ concepts like documentation, platform-independence / portability,
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RISC-V compatibility, _customization_ and _ease of use_ (see the <<_project_key_features>> below).
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RISC-V compatibility, _ extensibility & customization_ and _ease of use_ (see the <<_project_key_features>> below).
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Furthermore, the NEORV32 pays special focus on _execution safety_ using <<_full_virtualization>>. The CPU aims to
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Furthermore, the NEORV32 pays special focus on _execution safety_ using <<_full_virtualization>>. The CPU aims to
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provide fall-backs for _everything that could go wrong_. This includes malformed instruction words, privilege escalations
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provide fall-backs for _everything that could go wrong_. This includes malformed instruction words, privilege escalations
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and even memory accesses that are checked for address space holes and deterministic response times of memory-mapped
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and even memory accesses that are checked for address space holes and deterministic response times of memory-mapped
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devices. Precise exceptions allow a defined and fully-synchronized state of the CPU at every time an in every situation.
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devices. Precise exceptions allow a defined and fully-synchronized state of the CPU at every time an in every situation.
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