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Basically, the processor is a SoC consisting of the NEORV32 CPU, peripheral/IO devices, embedded
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Basically, the processor is a SoC consisting of the NEORV32 CPU, peripheral/IO devices, embedded
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memories, an external memory interface and a bus infrastructure to interconnect all units. Additionally, the
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memories, an external memory interface and a bus infrastructure to interconnect all units. Additionally, the
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system implements an internal reset generator and a global clock generator/divider.
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system implements an internal reset generator and a global clock generator/divider.
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**Internal Reset Generator**
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**Internal Reset Generator**
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[IMPORTANT]
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Most processor-internal modules - except for the CPU and the watchdog timer - do not have a dedicated
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Most processor-internal modules - except for the CPU and the watchdog timer - do not have a dedicated
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reset signal. However, all devices can be reset by software by clearing the corresponding unit's control
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reset signal. However, all devices can be reset by software by clearing the corresponding unit's control
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register. The automatically included application start-up code (`crt0.S`) will perform a software-reset of all
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register. The automatically included application start-up code (`crt0.S`) will perform a software-reset of all
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modules to ensure a clean system reset state.
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modules to ensure a clean system reset state.
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The hardware reset signal of the processor can either be
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The hardware reset signal of the processor can either be triggered via the external reset pin (`rstn_i`, low-active),
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triggered via the external reset pin (`rstn_i`, low-active) or by the internal watchdog timer (if implemented).
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by the internal watchdog timer (if implemented) or by the on-chip debugger. The external reset signal `rstn_i`
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Before the external reset signal is applied to the system, it is extended to have a minimal duration of eight
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is extended to be active for at least 4 cycles when triggered.
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clock cycles.
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**Internal Clock Divider**
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**Internal Clock Divider**
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An internal clock divider generates 8 clock signals derived from the processor's main clock input `clk_i`.
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An internal clock divider generates 8 clock signals derived from the processor's main clock input `clk_i`.
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These derived clock signals are not actual _clock signals_. Instead, they are derived from a simple counter and
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These derived clock signals are not actual _clock signals_. Instead, they are derived from a simple counter and
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|=======================
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|=======================
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| Prescaler bits: | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| Prescaler bits: | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| Resulting clock: | _f/2_ | _f/4_ | _f/8_ | _f/64_ | _f/128_ | _f/1024_| _f/2048_| _f/4096_
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| Resulting clock: | _f/2_ | _f/4_ | _f/8_ | _f/64_ | _f/128_ | _f/1024_| _f/2048_| _f/4096_
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|=======================
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|=======================
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**Peripheral / IO Devices**
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**Peripheral / IO Devices**
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The processor-internal peripheral/IO devices are located at the end of the 32-bit address space at base
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The processor-internal peripheral/IO devices are located at the end of the 32-bit address space at base
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address _0xFFFFFE00_. A region of 512 bytes is reserved for this devices. Hence, all peripheral/IO devices are
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address _0xFFFFFE00_. A region of 512 bytes is reserved for this devices. Hence, all peripheral/IO devices are
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accessed using a memory-mapped scheme. A special linker script as well as the NEORV32 core software
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accessed using a memory-mapped scheme. A special linker script as well as the NEORV32 core software
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register and register bit accesses.
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register and register bit accesses.
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[TIP]
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[TIP]
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A CMSIS-SVD-compatible **System View Description (SVD)** file including all peripherals is available in `sw/svd`.
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A CMSIS-SVD-compatible **System View Description (SVD)** file including all peripherals is available in `sw/svd`.
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**Interrupts of Processor-Internal Modules**
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**Interrupts of Processor-Internal Modules**
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Most peripheral/IO devices provide some kind of interrupt (for example to signal available incoming data). These
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Most peripheral/IO devices provide some kind of interrupt (for example to signal available incoming data). These
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interrupts are entirely mapped to the CPU's <<_custom_fast_interrupt_request_lines>>. Note that all these
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interrupts are entirely mapped to the CPU's <<_custom_fast_interrupt_request_lines>>. Note that all these
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interrupt lines are high-active and are permanently triggered until the IRQ-causing condition is resolved.
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interrupt lines are high-active and are permanently triggered until the IRQ-causing condition is resolved.
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**Nomenclature for the Peripheral / IO Devices Listing**
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**Nomenclature for the Peripheral / IO Devices Listing**
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Each peripheral device chapter features a register map showing accessible control and data registers of the
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Each peripheral device chapter features a register map showing accessible control and data registers of the
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according device including the implemented control and status bits. C-language code can directly interact with these
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according device including the implemented control and status bits. C-language code can directly interact with these
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registers via pre-defined `struct`. Each IO/peripheral module provides a unique `struct`. All accessible
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registers via pre-defined `struct`. Each IO/peripheral module provides a unique `struct`. All accessible
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