| Line 129... |
Line 129... |
value printed in light gray.
|
value printed in light gray.
|
|
|
[TIP]
|
[TIP]
|
The NEORV32 generics allow to configure the system according to your needs. The generics are
|
The NEORV32 generics allow to configure the system according to your needs. The generics are
|
used to control implementation of certain CPU extensions and peripheral modules and even allow to
|
used to control implementation of certain CPU extensions and peripheral modules and even allow to
|
optimize the system for certain design goals like minimal area or maximum performance.
|
optimize the system for certain design goals like minimal area or maximum performance. +
|
|
**More information can be found in the user guides' section
|
|
https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration]**.
|
|
|
[TIP]
|
[TIP]
|
Privileged software can determine the actual CPU and processor configuration via the `misa` and
|
Privileged software can determine the actual CPU and processor configuration via the `misa` and the
|
`mzext` (see <<_machine_trap_setup>> and <<_neorv32_specific_custom_csrs>>) CSRs and via the memory-mapped _SYSINFO_ module (see <<_system_configuration_information_memory_sysinfo>>),
|
i_SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
|
respectively.
|
|
|
|
[TIP]
|
[NOTE]
|
If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry **will not be synthesized at all**.
|
If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry
|
Hence, the disabled modules do not increase area and power requirements and do not impact the timing.
|
**will not be synthesized at all**. Hence, the disabled modules do not increase area and power requirements
|
|
and do not impact the timing.
|
|
|
[TIP]
|
[NOTE]
|
Not all configuration combinations are valid. The processor RTL code provides sanity checks to inform the user
|
Not all configuration combinations are valid. The processor RTL code provides sanity checks to inform the user
|
during synthesis/simulation if an invalid combination has been detected.
|
during synthesis/simulation if an invalid combination has been detected.
|
|
|
**Generic Description**
|
**Generic Description**
|
|
|
| Line 170... |
Line 172... |
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CLOCK_FREQUENCY** | _natural_ | _none_
|
| **CLOCK_FREQUENCY** | _natural_ | _none_
|
3+| The clock frequency of the processor's `clk_i` input port in Hertz (Hz).
|
3+| The clock frequency of the processor's `clk_i` input port in Hertz (Hz). This value can be retrieved by software
|
|
from the <<_system_configuration_information_memory_sysinfo, SYSINFO>> module.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _INT_BOOTLOADER_EN_
|
===== _INT_BOOTLOADER_EN_
|
| Line 188... |
Line 191... |
0x00000000) to the base address of the boot ROM. See section <<_boot_configuration>> for more information.
|
0x00000000) to the base address of the boot ROM. See section <<_boot_configuration>> for more information.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _USER_CODE_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **USER_CODE** | _std_ulogic_vector(31 downto 0)_ | x"00000000"
|
|
3+| Custom user code that can be read by software via the _SYSINFO_ module.
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _HW_THREAD_ID_
|
===== _HW_THREAD_ID_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **HW_THREAD_ID** | _natural_ | 0
|
| **HW_THREAD_ID** | _natural_ | 0
|
3+| The hart ID of the CPU. Can be read via the `mhartid` CSR. Hart IDs must be unique within a system.
|
3+| The hart ID of the CPU. Software can retrieve this value from the `mhartid` CSR.
|
|
Note that hart IDs must be unique within a system.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _ON_CHIP_DEBUGGER_EN_
|
===== _ON_CHIP_DEBUGGER_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **ON_CHIP_DEBUGGER_EN** | _boolean_ | false
|
| **ON_CHIP_DEBUGGER_EN** | _boolean_ | false
|
3+| Implement on-chip debugger (OCD). See chapter <<_on_chip_debugger_ocd>>.
|
3+| Implement the on-chip debugger (OCD) and the CPU debug mode.
|
|
See chapter <<_on_chip_debugger_ocd>> for more information.
|
|======
|
|======
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== RISC-V CPU Extensions
|
==== RISC-V CPU Extensions
|
|
|
See section <<_instruction_sets_and_extensions>> for more information.
|
[TIP]
|
|
See section <<_instruction_sets_and_extensions>> for more information. The configuration of the RISC-V _main_ ISA extensions
|
|
(like `M`) can be determined via the <<_misa>> CSR. The configuration of ISA _sub-extensions_ (like `Zicsr`) and _extension options_
|
|
can be determined via memory-mapped registers of the <<_system_configuration_information_memory_sysinfo>> module.
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_A_
|
===== _CPU_EXTENSION_RISCV_A_
|
|
|
| Line 246... |
Line 243... |
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_C** | _boolean_ | false
|
| **CPU_EXTENSION_RISCV_C** | _boolean_ | false
|
3+| Implement compressed instructions (16-bit) when _true_.
|
3+| Implement compressed instructions (16-bit) when _true_. Compressed instructions can reduce program code
|
See section <<_c_compressed_instructions>>.
|
size by approx. 30%. See section <<_c_compressed_instructions>>.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_E_
|
===== _CPU_EXTENSION_RISCV_E_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_E** | _boolean_ | false
|
| **CPU_EXTENSION_RISCV_E** | _boolean_ | false
|
3+| Implement the embedded CPU extension (only implement the first 16 data registers) when _true_.
|
3+| Implement the embedded CPU extension (only implement the first 16 data registers) when _true_. This reduces embedded memory
|
See section <<_e_embedded_cpu>>.
|
requirements for the register file. See section <<_e_embedded_cpu>> for more information. Note that this RISC-V extensions
|
|
requires a different application binary interface (ABI).
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_M_
|
===== _CPU_EXTENSION_RISCV_M_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_M** | _boolean_ | false
|
| **CPU_EXTENSION_RISCV_M** | _boolean_ | false
|
3+| Implement integer multiplication and division instructions when _true_.
|
3+| Implement hardware accelerators for integer multiplication and division instructions when _true_.
|
See section <<_m_integer_multiplication_and_division>>.
|
If this extensions is not enabled, multiplication and division operations (_not_ instructions) will be computed entirely in software.
|
|
If only a hardware multiplier is required use the <<_cpu_extension_riscv_zmmul>> extension. Multiplication can also be mapped
|
|
to DSP slices via the <<_fast_mul_en>> generic.
|
|
See section <<_m_integer_multiplication_and_division>> for more information.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_U_
|
===== _CPU_EXTENSION_RISCV_U_
|
| Line 283... |
Line 284... |
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_U** | _boolean_ | false
|
| **CPU_EXTENSION_RISCV_U** | _boolean_ | false
|
3+| Implement less-privileged user mode when _true_.
|
3+| Implement less-privileged user mode when _true_.
|
See section <<_u_less_privileged_user_mode>>.
|
See section <<_u_less_privileged_user_mode>> for more information.
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _CPU_EXTENSION_RISCV_Zbb_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **CPU_EXTENSION_RISCV_Zbb** | _boolean_ | false
|
|
3+| Implement the `Zbb` _basic_ bit-manipulation sub-extension when _true_.
|
|
See section <<_zbb_basic_bit_manipulation_operations>> for more information.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_Zfinx_
|
===== _CPU_EXTENSION_RISCV_Zfinx_
|
| Line 295... |
Line 308... |
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_Zfinx** | _boolean_ | false
|
| **CPU_EXTENSION_RISCV_Zfinx** | _boolean_ | false
|
3+| Implement the 32-bit single-precision floating-point extension (using integer registers) when _true_.
|
3+| Implement the 32-bit single-precision floating-point extension (using integer registers) when _true_.
|
See section <<_zfinx_single_precision_floating_point_operations>>.
|
See section <<_zfinx_single_precision_floating_point_operations>> for more information.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_Zicsr_
|
===== _CPU_EXTENSION_RISCV_Zicsr_
|
| Line 309... |
Line 322... |
|======
|
|======
|
| **CPU_EXTENSION_RISCV_Zicsr** | _boolean_ | true
|
| **CPU_EXTENSION_RISCV_Zicsr** | _boolean_ | true
|
3+| Implement the control and status register (CSR) access instructions when true. Note: When this option is
|
3+| Implement the control and status register (CSR) access instructions when true. Note: When this option is
|
disabled, the complete privileged architecture / trap system will be excluded from synthesis. Hence, no interrupts, no exceptions and
|
disabled, the complete privileged architecture / trap system will be excluded from synthesis. Hence, no interrupts, no exceptions and
|
no machine information will be available.
|
no machine information will be available.
|
See section <<_zicsr_control_and_status_register_access_privileged_architecture>>.
|
See section <<_zicsr_control_and_status_register_access_privileged_architecture>> for more information.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_Zifencei_
|
===== _CPU_EXTENSION_RISCV_Zifencei_
|
| Line 321... |
Line 334... |
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_Zifencei** | _boolean_ | false
|
| **CPU_EXTENSION_RISCV_Zifencei** | _boolean_ | false
|
3+| Implement the instruction fetch synchronization instruction `fence.i`. For example, this option is required
|
3+| Implement the instruction fetch synchronization instruction `fence.i`. For example, this option is required
|
for self-modifying code (and/or for i-cache flushes).
|
for self-modifying code (and/or for instruction cache and CPU prefetch buffer flushes).
|
See section <<_zifencei_instruction_stream_synchronization>>.
|
See section <<_zifencei_instruction_stream_synchronization>> for more information.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_Zmmul_
|
===== _CPU_EXTENSION_RISCV_Zmmul_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_Zmmul** | _boolean_ | false
|
| **CPU_EXTENSION_RISCV_Zmmul** | _boolean_ | false
|
3+| Implement integer multiplication-only instructions when _true_. This is a sub-extensions of the `M` extension.
|
3+| Implement integer multiplication-only instructions when _true_. This is a sub-extension of the `M` extension, which
|
See section <<_zmmul_integer_multiplication>>.
|
cannot be used together with the `M` extension. See section <<_zmmul_integer_multiplication>> for more information.
|
|======
|
|======
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
| Line 352... |
Line 365... |
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **FAST_MUL_EN** | _boolean_ | false
|
| **FAST_MUL_EN** | _boolean_ | false
|
3+| When this generic is enabled, the multiplier of the `M` extension is realized using DSPs blocks instead of an
|
3+| When this generic is enabled, the multiplier of the `M` extension is implemented using DSPs blocks instead of an
|
iterative bit-serial approach. This generic is only relevant when the multiplier and divider CPU extension is
|
iterative bit-serial approach. Performance will be increased and LUT utilization will be reduced at the cost of DSP slice
|
enabled (<<_cpu_extension_riscv_m>> is _true_).
|
utilization. This generic is only relevant when a hardware multiplier CPU extension is
|
|
enabled (<<_cpu_extension_riscv_m>> or <<_cpu_extension_riscv_zmmul>> is _true_). **Note that the multipliers of the
|
|
<<_zfinx_single_precision_floating_point_operations>> extension are always mapped to DSP block (if available).**
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _FAST_SHIFT_EN_
|
===== _FAST_SHIFT_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **FAST_SHIFT_EN** | _boolean_ | false
|
| **FAST_SHIFT_EN** | _boolean_ | false
|
3+| When this generic is set _true_ the shifter unit of the CPU's ALU is implemented as fast barrel shifter (requiring
|
3+| If this generic is set _true_ the shifter unit of the CPU's ALU is implemented as fast barrel shifter (requiring
|
more hardware resources). If it is set _false_ the CPU uses a serial shifter that only performs a single bit shift per cycle
|
more hardware resources but completing within two clock cycles). If it is set _false_, the CPU uses a serial shifter
|
(small but slow).
|
that only performs a single bit shift per cycle (requiring less hardware resources, but requires up to 32 clock
|
|
cycles to complete - depending on shift amount). **Note that this option also implements barrel shifters for _all_
|
|
shift-related operations of the <<_zbb_basic_bit_manipulation_operations>> extension.**
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_CNT_WIDTH_
|
===== _CPU_CNT_WIDTH_
|
| Line 379... |
Line 396... |
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_CNT_WIDTH** | _natural_ | 64
|
| **CPU_CNT_WIDTH** | _natural_ | 64
|
3+| This generic configures the total size of the CPU's `cycle` and `instret` CSRs (low word + high word).
|
3+| This generic configures the total size of the CPU's `cycle` and `instret` CSRs (low word + high word).
|
The maximum value is 64, the minimum value is 0. See
|
The maximum value is 64, the minimum value is 0. See section <<_machine_counters_and_timers>> for more information.
|
section <<_machine_counters_and_timers>> for more information. Note: configurations with <<_cpu_cnt_width>>
|
Note: configurations with <<_cpu_cnt_width>> less than 64 bits do not comply to the RISC-V specs.
|
less than 64 bits do not comply to the RISC-V specs.
|
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_IPB_ENTRIES_
|
===== _CPU_IPB_ENTRIES_
|
| Line 394... |
Line 410... |
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_IPB_ENTRIES** | _natural_ | 2
|
| **CPU_IPB_ENTRIES** | _natural_ | 2
|
3+| This generic configures the number of entries in the CPU's instruction prefetch buffer (a FIFO).
|
3+| This generic configures the number of entries in the CPU's instruction prefetch buffer (a FIFO).
|
The value has to be a power of two and has to be greater than zero.
|
The value has to be a power of two and has to be greater than zero.
|
Long linear sequences of code can benefit from an increased IPB size. For setups that use the instruction
|
Long linear sequences of code can benefit from an increased IPB size.
|
cache (<<_icache_en>>) this generic should be set to 1.
|
|
|======
|
|======
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
| Line 414... |
Line 429... |
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **PMP_NUM_REGIONS** | _natural_ | 0
|
| **PMP_NUM_REGIONS** | _natural_ | 0
|
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
|
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
|
protection logic will be implemented at all. Setting <<_pmp_num_regions>>_ > 0 will set the _CSR_MZEXT_PMP_ flag
|
protection logic will be implemented at all. Setting <<_pmp_num_regions>>_ > 0 will set the _SYSINFO_CPU_PMP_ flag
|
in the <<_mzext>> CSR.
|
in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _PMP_MIN_GRANULARITY_
|
===== _PMP_MIN_GRANULARITY_
|
| Line 444... |
Line 459... |
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **HPM_NUM_CNTS** | _natural_ | 0
|
| **HPM_NUM_CNTS** | _natural_ | 0
|
3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero no
|
3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero, no
|
hardware performance monitor logic will be implemented at all. Setting <<_hpm_num_cnts>> > 0 will set the _CSR_MZEXT_HPM_ flag
|
hardware performance monitor logic will be implemented at all. Setting <<_hpm_num_cnts>> > 0 will set the _SYSINFO_CPU_HPM_ flag
|
in the <<_mzext>> CSR.
|
in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _HPM_CNT_WIDTH_
|
===== _HPM_CNT_WIDTH_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **HPM_CNT_WIDTH** | _natural_ | 40
|
| **HPM_CNT_WIDTH** | _natural_ | 40
|
3+| This generic defines the total LSB-aligned size of each HPM counter (size(`[m]hpmcounter*h`) +
|
3+| This generic defines the total LSB-aligned size of each HPM counter (`size([m]hpmcounter*h)` +
|
size(`[m]hpmcounter*`)). The maximum value is 64, the minimal is 0. If the size is less than 64-bit, the
|
`size([m]hpmcounter*)`). The maximum value is 64, the minimal is 0. If the size is less than 64-bit, the
|
unused MSB-aligned counter bits are hardwired to zero.
|
unused MSB-aligned counter bits are hardwired to zero.
|
|======
|
|======
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
| Line 488... |
Line 503... |
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **MEM_INT_IMEM_SIZE** | _natural_ | 16*1024
|
| **MEM_INT_IMEM_SIZE** | _natural_ | 16*1024
|
3+| Size in bytes of the processor internal instruction memory (IMEM). Has no effect when _MEM_INT_IMEM_EN_ is _false_.
|
3+| Size in bytes of the processor internal instruction memory (IMEM). Has no effect when <<_mem_int_imem_en>> is _false_.
|
|======
|
|======
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
| Line 517... |
Line 532... |
|
|
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[cols="4,4,2"]
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[frame="all",grid="none"]
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[frame="all",grid="none"]
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|======
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|======
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| **MEM_INT_DMEM_SIZE** | _natural_ | 8*1024
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| **MEM_INT_DMEM_SIZE** | _natural_ | 8*1024
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3+| Size in bytes of the processor-internal data memory (DMEM). Has no effect when _MEM_INT_DMEM_EN_ is _false_.
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3+| Size in bytes of the processor-internal data memory (DMEM). Has no effect when <<_mem_int_dmem_en>> is _false_.
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|======
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|======
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// ####################################################################################################################
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// ####################################################################################################################
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[frame="all",grid="none"]
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|======
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|======
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| **ICACHE_EN** | _boolean_ | false
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| **ICACHE_EN** | _boolean_ | false
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3+| Implement processor internal instruction cache when _true_.
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3+| Implement processor internal instruction cache when _true_. Note: if the setup only uses processor-internal data
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and instruction memories there is not point of implementing the i-cache.
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|======
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|======
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===== _ICACHE_NUM_BLOCK_
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===== _ICACHE_NUM_BLOCK_
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|======
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|======
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| **ICACHE_NUM_BLOCKS** | _natural_ | 4
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| **ICACHE_NUM_BLOCKS** | _natural_ | 4
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3+| Number of blocks (cache "pages" or "lines") in the instruction cache. Has to be a power of two. Has no
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3+| Number of blocks (cache "pages" or "lines") in the instruction cache. Has to be a power of two. Has no
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effect when _ICACHE_DMEM_EN_ is false.
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effect when <<_icache_dmem_en>> is false.
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|======
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|======
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===== _ICACHE_BLOCK_SIZE_
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===== _ICACHE_BLOCK_SIZE_
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|======
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|======
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| **ICACHE_BLOCK_SIZE** | _natural_ | 64
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| **ICACHE_BLOCK_SIZE** | _natural_ | 64
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3+| Size in bytes of each block in the instruction cache. Has to be a power of two. Has no effect when
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3+| Size in bytes of each block in the instruction cache. Has to be a power of two. Has no effect when
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_ICACHE_EN_ is _false_.
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<<_icache_dmem_en>> is _false_.
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|======
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|======
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===== _ICACHE_ASSOCIATIVITY_
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===== _ICACHE_ASSOCIATIVITY_
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|======
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|======
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| **ICACHE_ASSOCIATIVITY** | _natural_ | 1
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| **ICACHE_ASSOCIATIVITY** | _natural_ | 1
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3+| Associativity (= number of sets) of the instruction cache. Has to be a power of two. Allowed configurations:
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3+| Associativity (= number of sets) of the instruction cache. Has to be a power of two. Allowed configurations:
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`1` = 1 set, direct mapped; `2` = 2-way set-associative. Has no effect when _ICACHE_EN_ is _false_.
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`1` = 1 set, direct mapped; `2` = 2-way set-associative. Has no effect when <<_icache_dmem_en>> is _false_.
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|======
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|======
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// ####################################################################################################################
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// ####################################################################################################################
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|======
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|======
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| **MEM_EXT_TIMEOUT** | _natural_ | 255
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| **MEM_EXT_TIMEOUT** | _natural_ | 255
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3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception. Set to 0 to disable auto-timeout.
|
3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception.
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If set to zero, there will be no auto-timeout and no bus fault exception (might permanently stall system!).
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|======
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|======
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===== _MEM_EXT_PIPE_MODE_
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===== _MEM_EXT_PIPE_MODE_
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[frame="all",grid="none"]
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|======
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|======
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| **MEM_EXT_PIPE_MODE** | _boolean_ | false
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| **MEM_EXT_PIPE_MODE** | _boolean_ | false
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3+| Use _standard_ ("classic") Wishbone protocol for external bus when _false_; use _pipelined_ Wishbone protocol when _true_.
|
3+| Use _standard_ ("classic") Wishbone protocol for external bus when _false_.
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Use _pipelined_ Wishbone protocol when _true_.
|
|======
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|======
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===== _MEM_EXT_BIG_ENDIAN_
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===== _MEM_EXT_BIG_ENDIAN_
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[frame="all",grid="none"]
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|======
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|======
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| **MEM_EXT_BIG_ENDIAN** | _boolean_ | false
|
| **MEM_EXT_BIG_ENDIAN** | _boolean_ | false
|
3+| Use BIG endian interface for external bus when _true_; use little endian interface when _false_.
|
3+| Use BIG endian interface for external bus when _true_. Use little endian interface when _false_.
|
|======
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|======
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===== _MEM_EXT_ASYNC_RX_
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===== _MEM_EXT_ASYNC_RX_
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|======
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|======
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| **MEM_EXT_ASYNC_RX** | _boolen_ | false
|
| **MEM_EXT_ASYNC_RX** | _boolen_ | false
|
3+| By default, _MEM_EXT_ASYNC_RX_ = _false_ implements a registered read-back path (RX) for incoming data in the bus interface
|
3+| By default, _MEM_EXT_ASYNC_RX_ = _false_ implements a registered read-back path (RX) for incoming data in the bus interface
|
in order to shorten the critical path. By setting _MEM_EXT_ASYNC_RX_ = _true_ an _asynchronous_ ("direct") read-back path is
|
in order to shorten the critical path. By setting _MEM_EXT_ASYNC_RX_ = _true_ an _asynchronous_ ("direct") read-back path is
|
implemented reducing access latency by one cycle.
|
implemented reducing access latency by one cycle but eventually increasing the critical path.
|
|======
|
|======
|
|
|
|
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// ####################################################################################################################
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// ####################################################################################################################
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|======
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|======
|
| **XIRQ_TRIGGER_TYPE** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
|
| **XIRQ_TRIGGER_TYPE** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
|
3+| Interrupt trigger type configuration (one bit for each IRQ channel): `0` = level-triggered, '1' = edge triggered.
|
3+| Interrupt trigger type configuration (one bit for each IRQ channel): `0` = level-triggered, '1' = edge triggered.
|
_XIRQ_TRIGGER_POLARITY_ generic is used to specify the actual level (high/low) or edge (falling/rising).
|
<<_xirq_trigger_polarity>> generic is used to specify the actual level (high/low) or edge (falling/rising).
|
|======
|
|======
|
|
|
|
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:sectnums!:
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:sectnums!:
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===== _XIRQ_TRIGGER_POLARITY_
|
===== _XIRQ_TRIGGER_POLARITY_
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|======
|
|======
|
| **XIRQ_TRIGGER_POLARITY** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
|
| **XIRQ_TRIGGER_POLARITY** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
|
3+| Interrupt trigger polarity configuration (one bit for each IRQ channel): `0` = low-level/falling-edge,
|
3+| Interrupt trigger polarity configuration (one bit for each IRQ channel): `0` = low-level/falling-edge,
|
'1' = high-level/rising-edge. _XIRQ_TRIGGER_TYPE_ generic is used to specify the actual type (level or edge).
|
'1' = high-level/rising-edge. <<_xirq_trigger_type>> generic is used to specify the actual type (level or edge).
|
|======
|
|======
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
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