| Line 24... |
Line 24... |
* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
|
* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
|
* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
|
* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
|
* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
|
* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
|
* _optional_ external interrupt controller with up to 32 channels (<<_external_interrupt_controller_xirq,**XIRQ**>>)
|
* _optional_ external interrupt controller with up to 32 channels (<<_external_interrupt_controller_xirq,**XIRQ**>>)
|
* _optional_ general purpose 32-bit timer (<<_general_purpose_timer_gptmr,**GPTMR**>>)
|
* _optional_ general purpose 32-bit timer (<<_general_purpose_timer_gptmr,**GPTMR**>>)
|
|
* _optional_ execute in place module (<<_execute_in_place_module_xip,**XIP**>>)
|
* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
|
* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
|
* bus keeper to monitor processor-internal bus transactions (<<_internal_bus_monitor_buskeeper,**BUSKEEPER**>>)
|
* bus keeper to monitor processor-internal bus transactions (<<_internal_bus_monitor_buskeeper,**BUSKEEPER**>>)
|
* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
|
* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
|
|
|
|
|
| Line 37... |
Line 38... |
=== Processor Top Entity - Signals
|
=== Processor Top Entity - Signals
|
|
|
The following table shows signals of the processor top entity (`rtl/core/neorv32_top.vhd`).
|
The following table shows signals of the processor top entity (`rtl/core/neorv32_top.vhd`).
|
The type of all signals is `std_ulogic` or `std_ulogic_vector`, respectively.
|
The type of all signals is `std_ulogic` or `std_ulogic_vector`, respectively.
|
|
|
[IMPORTAN]
|
.Default Values of Ports
|
|
[IMPORTANT]
|
All _input signals_ provide default values in case they are not explicitly assigned during instantiation.
|
All _input signals_ provide default values in case they are not explicitly assigned during instantiation.
|
For control signals the value `L` (weak pull-down) is used. For serial and parallel data signals
|
For control signals the value `L` (weak pull-down) is used. For serial and parallel data signals
|
the value `U` (unknown) is used. Pulled-down signals will not cause "accidental" system crashes
|
the value `U` (unknown) is used. Pulled-down signals will not cause "accidental" system crashes
|
since all control signals have defined level.
|
since all control signals have defined level.
|
|
|
|
.Configurable Amount of Channels
|
|
[IMPORTANT]
|
|
Some peripherals allow to configure the number of channels to-be-implemented by a generic (for example the number
|
|
of PWM or SLINK channels). The according input/output signals have a fixed sized regardless of the actually configured
|
|
amount of channels. If less than the maximum number of channels is configured, only the LSB-aligned channels are used:
|
|
in case of an _input port_ the remaining bits/channels are left unconnected; in case of an _output port_ the remaining
|
|
bits/channels are hardwired to zero.
|
|
|
[cols="<3,^2,^2,<11"]
|
[cols="<3,^2,^2,<11"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Signal | Width | Dir. | Function
|
| Signal | Width | Dir. | Function
|
4+^| **Global Control**
|
4+^| **Global Control**
|
| Line 71... |
Line 81... |
| `wb_ack_i` | 1 | in | transfer acknowledge
|
| `wb_ack_i` | 1 | in | transfer acknowledge
|
| `wb_err_i` | 1 | in | transfer error
|
| `wb_err_i` | 1 | in | transfer error
|
4+^| **Advanced Memory Control Signals**
|
4+^| **Advanced Memory Control Signals**
|
| `fence_o` | 1 | out | indicates an executed _fence_ instruction
|
| `fence_o` | 1 | out | indicates an executed _fence_ instruction
|
| `fencei_o` | 1 | out | indicates an executed _fencei_ instruction
|
| `fencei_o` | 1 | out | indicates an executed _fencei_ instruction
|
|
4+^| **Execute In Place Interface (<<_execute_in_place_module_xip,**XIP**>>)**
|
|
| `xip_csn_o` | 1 | out | chi select, low-active
|
|
| `xip_clk_o` | 1 | out | serial clock
|
|
| `xip_sdi_i` | 1 | in | serial data input
|
|
| `xip_sdo_o` | 1 | out | serial data output
|
4+^| **Stream Link Interface (<<_stream_link_interface_slink,SLINK>>)**
|
4+^| **Stream Link Interface (<<_stream_link_interface_slink,SLINK>>)**
|
| `slink_tx_dat_o` | 8x32 | out | TX link _n_ data
|
| `slink_tx_dat_o` | 8x32 | out | TX link _n_ data
|
| `slink_tx_val_o` | 8 | out | TX link _n_ data valid
|
| `slink_tx_val_o` | 8 | out | TX link _n_ data valid
|
| `slink_tx_rdy_i` | 8 | in | TX link _n_ allowed to send
|
| `slink_tx_rdy_i` | 8 | in | TX link _n_ allowed to send
|
| `slink_rx_dat_i` | 8x32 | in | RX link _n_ data
|
| `slink_rx_dat_i` | 8x32 | in | RX link _n_ data
|
| Line 100... |
Line 115... |
| `spi_csn_o` | 8 | out | SPI dedicated chip select (low-active)
|
| `spi_csn_o` | 8 | out | SPI dedicated chip select (low-active)
|
4+^| **Two-Wire Interface Controller (<<_two_wire_serial_interface_controller_twi,TWI>>)**
|
4+^| **Two-Wire Interface Controller (<<_two_wire_serial_interface_controller_twi,TWI>>)**
|
| `twi_sda_io` | 1 | inout | TWI serial data line
|
| `twi_sda_io` | 1 | inout | TWI serial data line
|
| `twi_scl_io` | 1 | inout | TWI serial clock line
|
| `twi_scl_io` | 1 | inout | TWI serial clock line
|
4+^| **Pulse-Width Modulation Channels (<<_pulse_width_modulation_controller_pwm,PWM>>)**
|
4+^| **Pulse-Width Modulation Channels (<<_pulse_width_modulation_controller_pwm,PWM>>)**
|
| `pwm_o` | 0..60 | out | pulse-width modulated channels
|
| `pwm_o` | 60 | out | pulse-width modulated channels
|
4+^| **Custom Functions Subsystem (<<_custom_functions_subsystem_cfs,CFS>>)**
|
4+^| **Custom Functions Subsystem (<<_custom_functions_subsystem_cfs,CFS>>)**
|
| `cfs_in_i` | 32 | in | custom CFS input signal conduit
|
| `cfs_in_i` | 32 | in | custom CFS input signal conduit
|
| `cfs_out_o` | 32 | out | custom CFS output signal conduit
|
| `cfs_out_o` | 32 | out | custom CFS output signal conduit
|
4+^| **Smart LED Interface - NeoPixel(TM) compatible (<<_smart_led_interface_neoled,NEOLED>>)**
|
4+^| **Smart LED Interface - NeoPixel(TM) compatible (<<_smart_led_interface_neoled,NEOLED>>)**
|
| `neoled_o` | 1 | out | asynchronous serial data output
|
| `neoled_o` | 1 | out | asynchronous serial data output
|
| Line 138... |
Line 153... |
|
|
[TIP]
|
[TIP]
|
Privileged software can determine the actual CPU and processor configuration via the `misa` and the
|
Privileged software can determine the actual CPU and processor configuration via the `misa` and the
|
<<_system_configuration_information_memory_sysinfo, SYSINFO>> registers.
|
<<_system_configuration_information_memory_sysinfo, SYSINFO>> registers.
|
|
|
|
[TIP]
|
|
Run a quick simulation using the provided simulation/GHDL scripts (https://stnolting.github.io/neorv32/ug/#_hello_world)
|
|
to verify the configuration of the processor generics is valid.
|
|
|
[NOTE]
|
[NOTE]
|
If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry
|
If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry
|
**will not be synthesized at all**. Hence, the disabled modules do not increase area and power requirements
|
**will not be synthesized at all**. Hence, the disabled modules do not increase area and power requirements
|
and do not impact the timing.
|
and do not impact the timing.
|
|
|
| Line 423... |
Line 442... |
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_CNT_WIDTH** | _natural_ | 64
|
| **CPU_CNT_WIDTH** | _natural_ | 64
|
3+| This generic configures the total size of the CPU's `[m]cycle` and `[m]instret` CSRs (low word + high word).
|
3+| This generic configures the total size of the CPU's `[m]cycle` and `[m]instret` CSRs (low word + high word).
|
The maximum value is 64, the minimum value is 0. See section <<_machine_counters_and_timers>> for more information.
|
The maximum value is 64, the minimum value is 0. See section <<_machine_counter_and_timer_csrs>> for more information.
|
This generic is only relevant if the `Zicntr` ISa extension is enabled (<<_cpu_extension_riscv_zicntr>>).
|
This generic is only relevant if the `Zicntr` ISa extension is enabled (<<_cpu_extension_riscv_zicntr>>).
|
Note: configurations with <<_cpu_cnt_width>> less than 64 bits do not comply to the RISC-V specs.
|
Note: configurations with <<_cpu_cnt_width>> less than 64 bits do not comply to the RISC-V specs.
|
|======
|
|======
|
|
|
|
|
| Line 584... |
Line 603... |
and instruction memories there is not point of implementing the i-cache.
|
and instruction memories there is not point of implementing the i-cache.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _ICACHE_NUM_BLOCK_
|
===== _ICACHE_NUM_BLOCKS_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **ICACHE_NUM_BLOCKS** | _natural_ | 4
|
| **ICACHE_NUM_BLOCKS** | _natural_ | 4
|
3+| Number of blocks (cache "pages" or "lines") in the instruction cache. Has to be a power of two. Has no
|
3+| Number of blocks (cache "pages" or "lines") in the instruction cache. Has to be a power of two. Has no
|
effect when <<_icache_dmem_en>> is false.
|
effect when <<_icache_en>> is false.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _ICACHE_BLOCK_SIZE_
|
===== _ICACHE_BLOCK_SIZE_
|
| Line 603... |
Line 622... |
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **ICACHE_BLOCK_SIZE** | _natural_ | 64
|
| **ICACHE_BLOCK_SIZE** | _natural_ | 64
|
3+| Size in bytes of each block in the instruction cache. Has to be a power of two. Has no effect when
|
3+| Size in bytes of each block in the instruction cache. Has to be a power of two. Has no effect when
|
<<_icache_dmem_en>> is _false_.
|
<<_icache_en>> is _false_.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _ICACHE_ASSOCIATIVITY_
|
===== _ICACHE_ASSOCIATIVITY_
|
| Line 615... |
Line 634... |
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **ICACHE_ASSOCIATIVITY** | _natural_ | 1
|
| **ICACHE_ASSOCIATIVITY** | _natural_ | 1
|
3+| Associativity (= number of sets) of the instruction cache. Has to be a power of two. Allowed configurations:
|
3+| Associativity (= number of sets) of the instruction cache. Has to be a power of two. Allowed configurations:
|
`1` = 1 set, direct mapped; `2` = 2-way set-associative. Has no effect when <<_icache_dmem_en>> is _false_.
|
`1` = 1 set, direct mapped; `2` = 2-way set-associative. Has no effect when <<_icache_en>> is _false_.
|
|======
|
|======
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
| Line 1027... |
Line 1046... |
3+| Implement general purpose 32-bit timer (GPTMR) when _true_.
|
3+| Implement general purpose 32-bit timer (GPTMR) when _true_.
|
See section <<_general_purpose_timer_gptmr>> for more information.
|
See section <<_general_purpose_timer_gptmr>> for more information.
|
|======
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _IO_XIP_EN_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **IO_XIP_EN** | _boolean_ | false
|
|
3+| Implement the execute in place module (XIP) when _true_.
|
|
See section <<_execute_in_place_module_xip>> for more information.
|
|
|======
|
|
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
=== Processor Interrupts
|
=== Processor Interrupts
|
| Line 1165... |
Line 1196... |
[IMPORTANT]
|
[IMPORTANT]
|
Please note that all processor-internal components including the peripheral/IO devices can also be
|
Please note that all processor-internal components including the peripheral/IO devices can also be
|
accessed from programs running in less-privileged user mode. For example, if the system relies on
|
accessed from programs running in less-privileged user mode. For example, if the system relies on
|
a periodic interrupt from the _MTIME_ timer unit, user-level programs could alter the _MTIME_
|
a periodic interrupt from the _MTIME_ timer unit, user-level programs could alter the _MTIME_
|
configuration corrupting this interrupt. This kind of security issues can be compensated using the
|
configuration corrupting this interrupt. This kind of security issues can be compensated using the
|
PMP system (see <<_machine_physical_memory_protection>>).
|
PMP system (see <<_machine_physical_memory_protection_csrs>>).
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Address Space Layout
|
==== Address Space Layout
|
|
|
| Line 1219... |
Line 1250... |
and byte (not for instruction fetch) quantities (requiring an accordingly aligned address).
|
and byte (not for instruction fetch) quantities (requiring an accordingly aligned address).
|
|
|
[TIP]
|
[TIP]
|
The following table shows the _default hardware-defined_ physical memory attributes of each main address space region.
|
The following table shows the _default hardware-defined_ physical memory attributes of each main address space region.
|
Additional user-defined attributes (for example certain read/write/execute rights for specific address space regions) can be
|
Additional user-defined attributes (for example certain read/write/execute rights for specific address space regions) can be
|
provided using the RISC-V <<_machine_physical_memory_protection>>.
|
provided using the RISC-V <<_machine_physical_memory_protection_csrs>>.
|
|
|
[cols="^1,^2,^2,^3,^2"]
|
[cols="^1,^2,^2,^3,^2"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| # | Region | Base address | Size | Attributes
|
| # | Region | Base address | Size | Attributes
|
| Line 1278... |
Line 1309... |
Any CPU access (data or instructions), which does not fulfill _at least one_ of the following conditions, is forwarded
|
Any CPU access (data or instructions), which does not fulfill _at least one_ of the following conditions, is forwarded
|
via the processor's bus interface to external components:
|
via the processor's bus interface to external components:
|
|
|
* access to the processor-internal IMEM and processor-internal IMEM is implemented
|
* access to the processor-internal IMEM and processor-internal IMEM is implemented
|
* access to the processor-internal DMEM and processor-internal DMEM is implemented
|
* access to the processor-internal DMEM and processor-internal DMEM is implemented
|
* access to the bootloader ROM and beyond → addresses >= _BOOTROM_BASE_ (default 0xFFFF0000) will never be forwarded to the external memory interface
|
* access to the bootloader ROM and beyond -> addresses >= _BOOTROM_BASE_ (default 0xFFFF0000) will never be forwarded to the external memory interface
|
|
|
|
[NOTE]
|
|
If the Execute In Place module (XIP) is implemented accesses map to this module are not forwarded to the
|
|
external memory interface. See section <<_execute_in_place_module_xip>> for more information.
|
|
|
If no (or not all) processor-internal memories are implemented, the according base addresses are mapped to external memories.
|
If no (or not all) processor-internal memories are implemented, the according base addresses are mapped to external memories.
|
For example, if the processor-internal IMEM is not implemented (<<_mem_int_imem_en>> = _false_), the processor will forward
|
For example, if the processor-internal IMEM is not implemented (<<_mem_int_imem_en>> = _false_), the processor will forward
|
any access to the instruction address space (starting at `ispace_base_c`) via the external bus interface to the external
|
any access to the instruction address space (starting at `ispace_base_c`) via the external bus interface to the external
|
memory system.
|
memory system.
|
| Line 1405... |
Line 1440... |
The base address of each component/module has to be aligned to the
|
The base address of each component/module has to be aligned to the
|
total size of the module's occupied address space! The occupied address space
|
total size of the module's occupied address space! The occupied address space
|
has to be a power of two (minimum 4 bytes)! Address spaces must not overlap!
|
has to be a power of two (minimum 4 bytes)! Address spaces must not overlap!
|
|
|
[IMPORTANT]
|
[IMPORTANT]
|
When accessing an IO device that hast not been implemented (via the according _IO_x_EN_ generic), a
|
When accessing an IO device that hast not been implemented (via the according generic), a
|
load/store access fault exception is triggered.
|
load/store access fault exception is triggered.
|
|
|
[IMPORTANT]
|
[IMPORTANT]
|
The peripheral/IO devices can only be written in full-word mode (i.e. 32-bit). Byte or half-word
|
The peripheral/IO devices can only be written in full-word mode (i.e. 32-bit). Byte or half-word
|
(8/16-bit) writes will trigger a store access fault exception. Read accesses are not size constrained.
|
(8/16-bit) writes will trigger a store access fault exception. Read accesses are not size constrained.
|
Processor-internal memories as well as modules connected to the external memory interface can still
|
Processor-internal memories as well as modules connected to the external memory interface can still
|
be written with a byte-wide granularity.
|
be written with a byte-wide granularity.
|
|
|
|
[NOTE]
|
|
Most of the IO devices do not have a hardware reset. Instead, the devices are reset via software by
|
|
writing zero to the unit's control register. A general software-based reset of all devices is done by the
|
|
application start-up code `crt0.S`.
|
|
|
[TIP]
|
[TIP]
|
You should use the provided core software library to interact with the peripheral devices. This
|
You should use the provided core software library to interact with the peripheral devices. This
|
prevents incompatibilities with future versions, since the hardware driver functions handle all the
|
prevents incompatibilities with future versions, since the hardware driver functions handle all the
|
register and register bit accesses.
|
register and register bit accesses.
|
|
|
[TIP]
|
[TIP]
|
A CMSIS-SVD-compatible **System View Description (SVD)** file including all peripherals is available in `sw/svd`.
|
A CMSIS-SVD-compatible **System View Description (SVD)** file including all peripherals is available in `sw/svd`.
|
|
|
[TIP]
|
|
Most of the IO devices do not have a hardware reset. Instead, the devices are reset via software by
|
|
writing zero to the unit's control register. A general software-based reset of all devices is done by the
|
|
application start-up code `crt0.S`.
|
|
|
|
**Interrupts of Processor-Internal Modules**
|
**Interrupts of Processor-Internal Modules**
|
|
|
Most peripheral/IO devices provide some kind of interrupt (for example to signal available incoming data). These
|
Most peripheral/IO devices provide some kind of interrupt (for example to signal available incoming data). These
|
interrupts are entirely mapped to the CPU's <<_custom_fast_interrupt_request_lines>>. Note that all these
|
interrupts are entirely mapped to the CPU's <<_custom_fast_interrupt_request_lines>>. Note that all these
|
interrupt lines are high-active and are permanently triggered until the IRQ-causing condition is resolved.
|
interrupt lines are high-active and are permanently triggered until the IRQ-causing condition is resolved.
|
| Line 1458... |
Line 1493... |
|
|
* `r/w` registers / bits can be read and written
|
* `r/w` registers / bits can be read and written
|
* `r/-` registers / bits are read-only; any write access to them has no effect
|
* `r/-` registers / bits are read-only; any write access to them has no effect
|
* `-/w` these registers / bits are write-only; they auto-clear in the next cycle and are always read as zero
|
* `-/w` these registers / bits are write-only; they auto-clear in the next cycle and are always read as zero
|
|
|
[TIP]
|
[NOTE]
|
Bits / registers that are not listed in the register map tables are not (yet) implemented. These registers
|
Bits / registers that are not listed in the register map tables are not (yet) implemented. These registers
|
/ bits are always read as zero. A write access to them has no effect, but user programs should only
|
/ bits are always read as zero. A write access to them has no effect, but user programs should only
|
write zero to them to keep compatible with future extension.
|
write zero to them to keep compatible with future extension.
|
|
|
[TIP]
|
[NOTE]
|
When writing to read-only registers, the access is nevertheless acknowledged, but no actual data is
|
When writing to read-only registers, the access is nevertheless acknowledged, but no actual data is
|
written. When reading data from a write-only register the result is undefined.
|
written. When reading data from a write-only register the result is undefined.
|
|
|
|
|
include::soc_imem.adoc[]
|
include::soc_imem.adoc[]
|
| Line 1506... |
Line 1541... |
|
|
include::soc_xirq.adoc[]
|
include::soc_xirq.adoc[]
|
|
|
include::soc_gptmr.adoc[]
|
include::soc_gptmr.adoc[]
|
|
|
|
include::soc_xip.adoc[]
|
|
|
include::soc_sysinfo.adoc[]
|
include::soc_sysinfo.adoc[]
|
