| Line 39... |
Line 39... |
|
|
The following table shows signals of the processor top entity (`rtl/core/neorv32_top.vhd`).
|
The following table shows signals of the processor top entity (`rtl/core/neorv32_top.vhd`).
|
The type of all signals is `std_ulogic` or `std_ulogic_vector`, respectively.
|
The type of all signals is `std_ulogic` or `std_ulogic_vector`, respectively.
|
|
|
.Default Values of Ports
|
.Default Values of Ports
|
[IMPORTANT]
|
[NOTE]
|
All _input signals_ provide default values in case they are not explicitly assigned during instantiation.
|
All _input signals_ provide default values in case they are not explicitly assigned during instantiation.
|
For control signals the value `L` (weak pull-down) is used. For serial and parallel data signals
|
For control signals the value `L` (weak pull-down) is used. For serial and parallel data signals
|
the value `U` (unknown) is used. Pulled-down signals will not cause "accidental" system crashes
|
the value `U` (unknown) is used. Pulled-down signals will not cause "accidental" system crashes
|
since all control signals have defined level.
|
since all control signals have defined level.
|
|
|
.Configurable Amount of Channels
|
.Configurable Amount of Channels
|
[IMPORTANT]
|
[NOTE]
|
Some peripherals allow to configure the number of channels to-be-implemented by a generic (for example the number
|
Some peripherals allow to configure the number of channels to-be-implemented by a generic (for example the number
|
of PWM or SLINK channels). The according input/output signals have a fixed sized regardless of the actually configured
|
of PWM or SLINK channels). The according input/output signals have a fixed sized regardless of the actually configured
|
amount of channels. If less than the maximum number of channels is configured, only the LSB-aligned channels are used:
|
amount of channels. If less than the maximum number of channels is configured, only the LSB-aligned channels are used:
|
in case of an _input port_ the remaining bits/channels are left unconnected; in case of an _output port_ the remaining
|
in case of an _input port_ the remaining bits/channels are left unconnected; in case of an _output port_ the remaining
|
bits/channels are hardwired to zero.
|
bits/channels are hardwired to zero.
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| Line 146... |
Line 146... |
|
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[TIP]
|
[TIP]
|
The NEORV32 generics allow to configure the system according to your needs. The generics are
|
The NEORV32 generics allow to configure the system according to your needs. The generics are
|
used to control implementation of certain CPU extensions and peripheral modules and even allow to
|
used to control implementation of certain CPU extensions and peripheral modules and even allow to
|
optimize the system for certain design goals like minimal area or maximum performance. +
|
optimize the system for certain design goals like minimal area or maximum performance. +
|
**More information can be found in the user guides' section
|
+
|
https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration]**.
|
More information can be found in the user guides' section
|
|
https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration].
|
|
|
[TIP]
|
[TIP]
|
Privileged software can determine the actual CPU and processor configuration via the `misa` and the
|
Privileged software can determine the actual CPU and processor configuration via the <<_misa>> and <<_mxisa>> CSRs (CPU)
|
<<_system_configuration_information_memory_sysinfo, SYSINFO>> registers.
|
and the <<_system_configuration_information_memory_sysinfo, SYSINFO>> (processor) memory-mapped registers.
|
|
|
[TIP]
|
[TIP]
|
Run a quick simulation using the provided simulation/GHDL scripts (https://stnolting.github.io/neorv32/ug/#_hello_world)
|
Run a quick simulation using the provided simulation/GHDL scripts (https://stnolting.github.io/neorv32/ug/#_hello_world)
|
to verify the configuration of the processor generics is valid.
|
to verify the configuration of the processor generics is valid.
|
|
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|
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[cols="4,4,2"]
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[cols="4,4,2"]
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[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **HW_THREAD_ID** | _natural_ | 0
|
| **HW_THREAD_ID** | _natural_ | 0
|
3+| The hart ID of the CPU. Software can retrieve this value from the `mhartid` CSR.
|
3+| The hart ID of the CPU. Software can retrieve this value from the <<_mhartid>> CSR.
|
Note that hart IDs must be unique within a system.
|
Note that hart IDs must be unique within a system.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
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:sectnums!:
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| Line 238... |
Line 239... |
|
|
// ####################################################################################################################
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// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== RISC-V CPU Extensions
|
==== RISC-V CPU Extensions
|
|
|
|
.Discovering ISA Extensions
|
[TIP]
|
[TIP]
|
See section <<_instruction_sets_and_extensions>> for more information. The configuration of the RISC-V _main_ ISA extensions
|
See section <<_instruction_sets_and_extensions>> for more information. The configuration of the RISC-V _main_ ISA extensions
|
(like `M`) can be determined via the <<_misa>> CSR. The configuration of ISA _sub-extensions_ (like `Zicsr`) and _extension options_
|
(like `M`) can be determined via the <<_misa>> CSR. The configuration of ISA _sub-extensions_ (like `Zicsr`) and _tuning options_
|
can be determined via memory-mapped registers of the <<_system_configuration_information_memory_sysinfo>> module.
|
can be determined via the NEORV32-specific <<_mxisa>> CSR.
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_EXTENSION_RISCV_A_
|
===== _CPU_EXTENSION_RISCV_A_
|
|
|
| Line 353... |
Line 355... |
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_Zicntr** | _boolean_ | true
|
| **CPU_EXTENSION_RISCV_Zicntr** | _boolean_ | true
|
3+| Implement the basic CPU counter CSRs (`time[h]`, `[m]cycle[h]`, `[m]instret[h]`) when true.
|
3+| Implement the basic CPU <<_machine_counter_and_timer_csrs>> (`time[h]`, `[m]cycle[h]`, `[m]instret[h]`) when true.
|
Enabling this extension will set the _SYSINFO_CPU_ZICNTR_ flag in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
|
|
See section <<_zicntr_cpu_base_counters>> for more information.
|
See section <<_zicntr_cpu_base_counters>> for more information.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
| Line 367... |
Line 368... |
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_EXTENSION_RISCV_Zihpm** | _boolean_ | false
|
| **CPU_EXTENSION_RISCV_Zihpm** | _boolean_ | false
|
3+| Implement hardware performance monitor CSRs when true.
|
3+| Implement hardware performance monitor CSRs when true.
|
Enabling this extension will set the _SYSINFO_CPU_ZIHPM_ flag in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
|
|
See section <<_zihpm_hardware_performance_monitors>> for more information.
|
See section <<_zihpm_hardware_performance_monitors>> for more information.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
| Line 397... |
Line 397... |
3+| Implement integer multiplication-only instructions when _true_. This is a sub-extension of the `M` extension, which
|
3+| Implement integer multiplication-only instructions when _true_. This is a sub-extension of the `M` extension, which
|
cannot be used together with the `M` extension. See section <<_zmmul_integer_multiplication>> for more information.
|
cannot be used together with the `M` extension. See section <<_zmmul_integer_multiplication>> for more information.
|
|======
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _CPU_EXTENSION_RISCV_Zxcfu_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **CPU_EXTENSION_RISCV_Zxcfu** | _boolean_ | false
|
|
3+| NEORV32-specific "custom RISC-V" ISA extensions: Implement the <<_custom_functions_unit_cfu>> for user-defined
|
|
custom instruction when _true_. See section <<_zxcfu_custom_instructions_extension_cfu>> for more information.
|
|
|======
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== Extension Options
|
==== Tuning Options
|
|
|
|
These are generics to fine-tune certain ISA extensions and CPU features.
|
See section <<_instruction_sets_and_extensions>> for more information.
|
See section <<_instruction_sets_and_extensions>> for more information.
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _FAST_MUL_EN_
|
===== _FAST_MUL_EN_
|
| Line 476... |
Line 489... |
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **PMP_NUM_REGIONS** | _natural_ | 0
|
| **PMP_NUM_REGIONS** | _natural_ | 0
|
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
|
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
|
protection logic will be implemented at all. Setting <<_pmp_num_regions>>_ > 0 will set the _SYSINFO_CPU_PMP_ flag
|
protection logic will be implemented at all.
|
in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
|
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _PMP_MIN_GRANULARITY_
|
===== _PMP_MIN_GRANULARITY_
|
| Line 1087... |
Line 1099... |
|=======================
|
|=======================
|
|
|
.Trigger type
|
.Trigger type
|
[IMPORTANT]
|
[IMPORTANT]
|
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
|
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
|
be explicitly cleared by setting the according `mip` CSR bit.
|
be explicitly cleared by setting the according <<_mip>> CSR bit.
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Platform External Interrupts
|
==== Platform External Interrupts
|
|
|
| Line 1146... |
Line 1158... |
|=======================
|
|=======================
|
|
|
.Trigger type
|
.Trigger type
|
[IMPORTANT]
|
[IMPORTANT]
|
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
|
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
|
be explicitly cleared by setting the according `mip` CSR bit.
|
be explicitly cleared by setting the according <<_mip>> CSR bit.
|
|
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
| Line 1170... |
Line 1182... |
5. **IO/peripheral address space**. Also a _fixed_ section used for the processor-internal memory-mapped IO/peripheral devices (e.g., UART).
|
5. **IO/peripheral address space**. Also a _fixed_ section used for the processor-internal memory-mapped IO/peripheral devices (e.g., UART).
|
|
|
.NEORV32 processor - address space (default configuration)
|
.NEORV32 processor - address space (default configuration)
|
image::address_space.png[900]
|
image::address_space.png[900]
|
|
|
|
.RAM Layout - Usage of the Data Address Space
|
|
[TIP]
|
|
The actual usage of the data address space by the software/executables (stack, heap, ...) is
|
|
illustrated in section <<_ram_layout>>.
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== CPU Data and Instruction Access
|
==== CPU Data and Instruction Access
|
|
|
The CPU can access all of the 4GB address space from the instruction fetch interface (**I**) and also from the
|
The CPU can access all of the 4GB address space from the instruction fetch interface (**I**) and also from the
|
