| Line 488... |
Line 488... |
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[cols="4,4,2"]
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[cols="4,4,2"]
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[frame="all",grid="none"]
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[frame="all",grid="none"]
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|======
|
|======
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| **PMP_NUM_REGIONS** | _natural_ | 0
|
| **PMP_NUM_REGIONS** | _natural_ | 0
|
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
|
3+| Total number of implemented protection regions (0..16). If this generics is zero no physical memory
|
protection logic will be implemented at all.
|
protection logic will be implemented at all.
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|======
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|======
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|
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:sectnums!:
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:sectnums!:
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===== _PMP_MIN_GRANULARITY_
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===== _PMP_MIN_GRANULARITY_
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[cols="4,4,2"]
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[cols="4,4,2"]
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[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **PMP_MIN_GRANULARITY** | _natural_ | 64*1024
|
| **PMP_MIN_GRANULARITY** | _natural_ | 4
|
3+| Minimal region granularity in bytes. Has to be a power of two. Has to be at least 8 bytes.
|
3+| Minimal region granularity in bytes. Has to be a power of two and has to be at least 4 bytes. A larger granularity
|
|
will reduce hardware utilization and impact on critical path but will also reduce the minimal region size.
|
|======
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|======
|
|
|
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// ####################################################################################################################
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// ####################################################################################################################
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:sectnums:
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:sectnums:
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| Line 1099... |
Line 1100... |
|=======================
|
|=======================
|
|
|
.Trigger type
|
.Trigger type
|
[IMPORTANT]
|
[IMPORTANT]
|
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
|
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
|
be explicitly cleared by setting the according <<_mip>> CSR bit.
|
be explicitly cleared by writing zero to the according <<_mip>> CSR bit.
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Platform External Interrupts
|
==== Platform External Interrupts
|
|
|
| Line 1158... |
Line 1159... |
|=======================
|
|=======================
|
|
|
.Trigger type
|
.Trigger type
|
[IMPORTANT]
|
[IMPORTANT]
|
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
|
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
|
be explicitly cleared by setting the according <<_mip>> CSR bit.
|
be explicitly cleared by writing zero to the according <<_mip>> CSR bit.
|
|
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
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| Line 1245... |
Line 1246... |
applications - even if the bootloader or all IO devices are not implemented - without modifying the core's
|
applications - even if the bootloader or all IO devices are not implemented - without modifying the core's
|
hardware sources.
|
hardware sources.
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Physical Memory Attributes
|
|
|
|
The processor setup defines fixed attributes for the four processor-internal address space regions.
|
|
Accessing a memory region in a way that violates any of these attributes will raise an according
|
|
access exception..
|
|
|
|
* `r` - read access (from CPU data access interface, "loads")
|
|
* `w` - write access (from CPU data access interface, "stores")
|
|
* `x` - execute access (from CPU instruction fetch interface)
|
|
* `a` - atomic access (from CPU data access interface)
|
|
* `8` - byte (8-bit)-accessible (when writing)
|
|
* `16` - half-word (16-bit)-accessible (when writing)
|
|
* `32` - word (32-bit)-accessible (when writing)
|
|
|
|
[NOTE]
|
|
Read accesses (loads and instruction fetches) can always access data in
|
|
word, half-word (for instruction fetch only if `C` extension is enabled)
|
|
and byte (not for instruction fetch) quantities (requiring an accordingly aligned address).
|
|
|
|
[TIP]
|
|
The following table shows the _default hardware-defined_ physical memory attributes of each main address space region.
|
|
Additional user-defined attributes (for example certain read/write/execute rights for specific address space regions) can be
|
|
provided using the RISC-V <<_machine_physical_memory_protection_csrs>>.
|
|
|
|
[cols="^1,^2,^2,^3,^2"]
|
|
[options="header",grid="rows"]
|
|
|=======================
|
|
| # | Region | Base address | Size | Attributes
|
|
| 5 | IO/peripheral devices | 0xfffffe00 | 512 bytes | `r/w/a/32`
|
|
| 4 | On-chip debugger | 0xfffff800 | 512 bytes | `r/w/x/32`
|
|
| 3 | Bootloader ROM | 0xffff0000 | up to 32kB | `r/x/a`
|
|
| 2 | DMEM | 0x80000000 | up to "2GB" | `r/w/x/a/8/16/32`
|
|
| 1 | IMEM | 0x00000000 | up to 2GB | `r/w/x/a/8/16/32`
|
|
|=======================
|
|
|
|
|
|
:sectnums:
|
|
==== Memory Configuration
|
==== Memory Configuration
|
|
|
The NEORV32 Processor was designed to provide maximum flexibility for the memory configuration.
|
The NEORV32 Processor was designed to provide maximum flexibility for the memory configuration.
|
The processor can populate the _instruction address space_ and/or the _data address space_ with **internal memories**
|
The processor can populate the _instruction address space_ and/or the _data address space_ with **internal memories**
|
for instructions (IMEM) and data (DMEM). Processor **external memories** can be used as an _alternative_ or even _in combination_ with
|
for instructions (IMEM) and data (DMEM). Processor **external memories** can be used as an _alternative_ or even _in combination_ with
|
| Line 1451... |
Line 1415... |
The processor-internal peripheral/IO devices are located at the end of the 32-bit address space at base
|
The processor-internal peripheral/IO devices are located at the end of the 32-bit address space at base
|
address _0xFFFFFE00_. A region of 512 bytes is reserved for this devices. Hence, all peripheral/IO devices are
|
address _0xFFFFFE00_. A region of 512 bytes is reserved for this devices. Hence, all peripheral/IO devices are
|
accessed using a memory-mapped scheme. A special linker script as well as the NEORV32 core software
|
accessed using a memory-mapped scheme. A special linker script as well as the NEORV32 core software
|
library abstract the specific memory layout for the user.
|
library abstract the specific memory layout for the user.
|
|
|
|
.Address Space Mapping
|
[IMPORTANT]
|
[IMPORTANT]
|
The base address of each component/module has to be aligned to the
|
The base address of each component/module has to be aligned to the
|
total size of the module's occupied address space! The occupied address space
|
total size of the module's occupied address space! The occupied address space
|
has to be a power of two (minimum 4 bytes)! Address spaces must not overlap!
|
has to be a power of two (minimum 4 bytes)! Address spaces must not overlap!
|
|
|
|
.Full-Word Write Accesses Only
|
[IMPORTANT]
|
[IMPORTANT]
|
When accessing an IO device that hast not been implemented (via the according generic), a
|
All peripheral/IO devices can only be written in full-word mode (i.e. 32-bit). Byte or half-word
|
load/store access fault exception is triggered.
|
|
|
|
[IMPORTANT]
|
|
The peripheral/IO devices can only be written in full-word mode (i.e. 32-bit). Byte or half-word
|
|
(8/16-bit) writes will trigger a store access fault exception. Read accesses are not size constrained.
|
(8/16-bit) writes will trigger a store access fault exception. Read accesses are not size constrained.
|
Processor-internal memories as well as modules connected to the external memory interface can still
|
Processor-internal memories as well as modules connected to the external memory interface can still
|
be written with a byte-wide granularity.
|
be written with a byte-wide granularity.
|
|
|
|
.Unimplemented Modules
|
|
[NOTE]
|
|
When accessing an IO device that hast not been implemented (via the according generic), a
|
|
load/store access fault exception is triggered.
|
|
|
|
.Hardware Reset
|
[NOTE]
|
[NOTE]
|
Most of the IO devices do not have a hardware reset. Instead, the devices are reset via software by
|
Most of the IO devices do not have a hardware reset. Instead, the devices are reset via software by
|
writing zero to the unit's control register. A general software-based reset of all devices is done by the
|
writing zero to the unit's control register. A general software-based reset of all devices is done by the
|
application start-up code `crt0.S`.
|
application start-up code `crt0.S`.
|
|
|
