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| CPU interrupts: | fast IRQ channel 1 | CFS interrupt (see <<_processor_interrupts>>)
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| CPU interrupts: | fast IRQ channel 1 | CFS interrupt (see <<_processor_interrupts>>)
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|=======================
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|=======================
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**Theory of Operation**
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**Theory of Operation**
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The custom functions subsystem can be used to implement application-specific user-defined co-processors
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The custom functions subsystem is meant for implementing application-specific user-defined co-processors
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(like encryption or arithmetic accelerators) or peripheral/communication interfaces. In contrast to connecting
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IP footnote:[Intellectual IP; proprietary circuit blocks.] blocks. The CFS provides up to 32x 32-bit memory-mapped
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custom hardware accelerators via the external memory interface, the CFS provide a convenient and low-latency
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registers (`REG`, see register map table below) that can be accessed by the CPU via normal load/store operations.
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extension and customization option.
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The actual functionality of these register has to be defined by the hardware designer. Furthermore, the CFS
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provides two IO conduits to implement custom module- or chip-external interfaces.
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The CFS provides up to 32x 32-bit memory-mapped registers `REG` (see register map table below). The actual
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functionality of these register has to be defined by the hardware designer.
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In contrast to connecting custom hardware accelerators via external memory interfaces (like SPI or the processor's
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external bus interface), the CFS provide a convenient, low-latency and tightly-coupled extension and
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customization option.
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Just like any other externally-connected IP, logic implemented within the custom functions subsystem can operate
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_independently_ of the CPU providing true parallel processing capabilities. Potential use cases might include
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dedicated hardware accelerators for en-/decryption (AES), signal processing (FFT) or AI applications
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(CNNs) as well as custom IO systems like fast memory interfaces (DDR) and mass storage (SDIO), networking (CAN)
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or real-time data transport (I2S).
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[INFO]
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[INFO]
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Take a look at the template CFS VHDL source file (`rtl/core/neorv32_cfs.vhd`). The file is highly
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Take a look at the template CFS VHDL source file (`rtl/core/neorv32_cfs.vhd`). The file is highly
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commented to illustrate all aspects that are relevant for implementing custom CFS-based co-processor designs.
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commented to illustrate all aspects that are relevant for implementing custom CFS-based co-processor designs.
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**CFS Software Access**
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**CFS Software Access**
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The CFS memory-mapped registers can be accessed by software using the provided C-language aliases (see
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The CFS memory-mapped registers can be accessed by software using the provided C-language aliases (see
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register map table below). Note that all interface registers provide 32-bit access data of type `uint32_t`.
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register map table below). Note that all interface registers provide 32-bit access data of type `uint32_t`.
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// C-code CFS usage example
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// C-code CFS usage example
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NEORV32_CFS.REG[0] = (uint32_t)some_data_array(i); // write to CFS register 0
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NEORV32_CFS.REG[0] = (uint32_t)some_data_array(i); // write to CFS register 0
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uint32_t temp = NEORV32_CFS.REG[20]; // read from CFS register 20
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uint32_t temp = NEORV32_CFS.REG[20]; // read from CFS register 20
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----
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----
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**CFS Interrupt**
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**CFS Interrupt**
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The CFS provides a single one-shot interrupt request signal mapped to the CPU's fast interrupt channel 1.
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The CFS provides a single high-level-triggered interrupt request signal mapped to the CPU's fast interrupt channel 1.
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See section <<_processor_interrupts>> for more information.
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Once set, the interrupt has to stay asserted until explicitly acknowledged by the software (for example by
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writing to a specific CFS register). See section <<_processor_interrupts>> for more information.
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**CFS Configuration Generic**
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**CFS Configuration Generic**
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By default, the CFS provides a single 32-bit `std_(u)logic_vector` configuration generic _IO_CFS_CONFIG_
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By default, the CFS provides a single 32-bit `std_(u)logic_vector` configuration generic _IO_CFS_CONFIG_
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that is available in the processor's top entity. This generic can be used to pass custom configuration options
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that is available in the processor's top entity. This generic can be used to pass custom configuration options
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from the top entity down to the CFS entity.
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from the top entity directly down to the CFS. The actual definition of the generics and it'S usage inside the
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CFS is left to the hardware designer.
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**CFS Custom IOs**
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**CFS Custom IOs**
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By default, the CFS also provides two unidirectional input and output conduits `cfs_in_i` and `cfs_out_o`.
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By default, the CFS also provides two unidirectional input and output conduits `cfs_in_i` and `cfs_out_o`.
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These signals are propagated to the processor's top entity. The actual use of these signals has to be defined
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These signals are directly propagated to the processor's top entity. These conduits can be used to implement
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by the hardware designer. The size of the input signal conduit `cfs_in_i` is defined via the (top's) _IO_CFS_IN_SIZE_ configuration
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application-specific interfaces like memory or network connections. The actual use case of these signals
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generic (default = 32-bit). The size of the output signal conduit `cfs_out_o` is defined via the (top's)
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has to be defined by the hardware designer.
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The size of the input signal conduit `cfs_in_i` is defined via the top's _IO_CFS_IN_SIZE_ configuration
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generic (default = 32-bit). The size of the output signal conduit `cfs_out_o` is defined via the top's
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_IO_CFS_OUT_SIZE_ configuration generic (default = 32-bit). If the custom function subsystem is not implemented
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_IO_CFS_OUT_SIZE_ configuration generic (default = 32-bit). If the custom function subsystem is not implemented
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(_IO_CFS_EN_ = false) the `cfs_out_o` signal is tied to all-zero.
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(_IO_CFS_EN_ = false) the `cfs_out_o` signal is tied to all-zero.
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.CFS register map (`struct NEORV32_CFS`)
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.CFS register map (`struct NEORV32_CFS`)
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[cols="^4,<5,^2,^3,<14"]
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[cols="^4,<5,^2,^3,<14"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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|=======================
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|=======================
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| Address | Name [C] | Bit(s) | R/W | Function
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| Address | Name [C] | Bit(s) | R/W | Function
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