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_independently_ of the CPU providing true parallel processing capabilities. Potential use cases might include
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_independently_ of the CPU providing true parallel processing capabilities. Potential use cases might include
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dedicated hardware accelerators for en-/decryption (AES), signal processing (FFT) or AI applications
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dedicated hardware accelerators for en-/decryption (AES), signal processing (FFT) or AI applications
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(CNNs) as well as custom IO systems like fast memory interfaces (DDR) and mass storage (SDIO), networking (CAN)
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(CNNs) as well as custom IO systems like fast memory interfaces (DDR) and mass storage (SDIO), networking (CAN)
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or real-time data transport (I2S).
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or real-time data transport (I2S).
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[INFO]
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[TIP]
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If you like to implement _custom instructions_ that are executed right within the CPU's ALU
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see the <<_zxcfu_custom_instructions_extension_cfu>> and the according <<_custom_functions_unit_cfu>>.
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[TIP]
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Take a look at the template CFS VHDL source file (`rtl/core/neorv32_cfs.vhd`). The file is highly
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Take a look at the template CFS VHDL source file (`rtl/core/neorv32_cfs.vhd`). The file is highly
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commented to illustrate all aspects that are relevant for implementing custom CFS-based co-processor designs.
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commented to illustrate all aspects that are relevant for implementing custom CFS-based co-processor designs.
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**CFS Software Access**
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**CFS Software Access**
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