| Line 6... |
Line 6... |
[frame="topbot",grid="none"]
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[frame="topbot",grid="none"]
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|=======================
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|=======================
|
| Hardware source file(s): | neorv32_gpio.vhd |
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| Hardware source file(s): | neorv32_gpio.vhd |
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| Software driver file(s): | neorv32_gpio.c |
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| Software driver file(s): | neorv32_gpio.c |
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| | neorv32_gpio.h |
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| | neorv32_gpio.h |
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| Top entity port: | `gpio_o` | 32-bit parallel output port
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| Top entity port: | `gpio_o` | 64-bit parallel output port
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| | `gpio_i` | 32-bit parallel input port
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| | `gpio_i` | 64-bit parallel input port
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| Configuration generics: | _IO_GPIO_EN_ | implement GPIO port when _true_
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| Configuration generics: | _IO_GPIO_EN_ | implement GPIO port when _true_
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| CPU interrupts: | FIRQ channel 8 | pin-change interrupt (see <<_processor_interrupts>>)
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| CPU interrupts: | none |
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|=======================
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|=======================
|
|
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**Theory of Operation**
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**Theory of Operation**
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|
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The general purpose parallel IO port unit provides a simple 32-bit parallel input port and a 32-bit parallel
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The general purpose parallel IO port unit provides a simple 64-bit parallel input port and a 64-bit parallel
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output port. These ports can be used chip-externally (for example to drive status LEDs, connect buttons, etc.)
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output port. These ports can be used chip-externally (for example to drive status LEDs, connect buttons, etc.)
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or system-internally to provide control signals for other IP modules. When the modules is disabled for
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or system-internally to provide control signals for other IP modules. The component is disabled for
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implementation the GPIO output port is tied to zero.
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implementation when the _IO_GPIO_EN_ generic is set _false_. In this case GPIO output port is tied to all-zero.
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**Pin-Change Interrupt**
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.Access atomicity
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[NOTE]
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The parallel input port `gpio_i` features a single pin-change interrupt. Whenever an input pin has a low-to-high
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The GPIO modules uses two memory-mapped registers (each 32-bit) each for accessing the input and
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or high-to-low transition, the interrupt is triggered. By default, the pin-change interrupt is disabled and
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output signals. Since the CPU can only process 32-bit "at once" updating the entire output cannot
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can be enabled using a bit mask that has to be written to the _GPIO_INPUT_ register. Each set bit in this mask
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be performed within a single clock cycle.
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enables the pin-change interrupt for the corresponding input pin. If more than one input pin is enabled for
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triggering the pin-change interrupt, any transition on one of the enabled input pins will trigger the CPU's pinchange
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interrupt. If the modules is disabled for implementation, the pin-change interrupt is also permanently
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disabled.
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.GPIO unit register map
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.GPIO unit register map
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[cols="<2,<2,^1,^1,<6"]
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[cols="<2,<2,^1,^1,<6"]
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
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| Address | Name [C] | Bit(s) | R/W | Function
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| Address | Name [C] | Bit(s) | R/W | Function
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.2+<| `0xffffff80` .2+<| _GPIO_INPUT_ ^| 31:0 ^| r/- <| parallel input port
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| `0xffffffc0` | _GPIO_INPUT_LO_ | 31:0 | r/- | parallel input port pins 31:0 (write accesses are ignored)
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^| 31:0 ^| -/w <| parallel input pin-change IRQ enable mask
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| `0xffffffc4` | _GPIO_INPUT_HI_ | 31:0 | r/- | parallel input port pins 63:32 (write accesses are ignored)
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| `0xffffff84` | _GPIO_OUTPUT_ | 31:0 | r/w | parallel output port
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| `0xffffffc8` | _GPIO_OUTPUT_LO_ | 31:0 | r/w | parallel output port pins 31:0
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| `0xffffffcc` | _GPIO_OUTPUT_HI_ | 31:0 | r/w | parallel output port pins 63:32
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|=======================
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|=======================
|
