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[NOTE]
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[NOTE]
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The GPIO modules uses two memory-mapped registers (each 32-bit) each for accessing the input and
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The GPIO modules uses two memory-mapped registers (each 32-bit) each for accessing the input and
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output signals. Since the CPU can only process 32-bit "at once" updating the entire output cannot
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output signals. Since the CPU can only process 32-bit "at once" updating the entire output cannot
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be performed within a single clock cycle.
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be performed within a single clock cycle.
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.GPIO unit register map
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.GPIO unit register map (`struct NEORV32_GPIO`)
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[cols="<2,<2,^1,^1,<6"]
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[cols="<2,<2,^1,^1,<6"]
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
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| Address | Name [C] | Bit(s) | R/W | Function
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| Address | Name [C] | Bit(s) | R/W | Function
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| `0xffffffc0` | _GPIO_INPUT_LO_ | 31:0 | r/- | parallel input port pins 31:0 (write accesses are ignored)
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| `0xffffffc0` | `NEORV32_GPIO.INPUT_LO` | 31:0 | r/- | parallel input port pins 31:0 (write accesses are ignored)
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| `0xffffffc4` | _GPIO_INPUT_HI_ | 31:0 | r/- | parallel input port pins 63:32 (write accesses are ignored)
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| `0xffffffc4` | `NEORV32_GPIO.INPUT_HI` | 31:0 | r/- | parallel input port pins 63:32 (write accesses are ignored)
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| `0xffffffc8` | _GPIO_OUTPUT_LO_ | 31:0 | r/w | parallel output port pins 31:0
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| `0xffffffc8` | `NEORV32_GPIO.OUTPUT_LO` | 31:0 | r/w | parallel output port pins 31:0
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| `0xffffffcc` | _GPIO_OUTPUT_HI_ | 31:0 | r/w | parallel output port pins 63:32
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| `0xffffffcc` | `NEORV32_GPIO.OUTPUT_HI` | 31:0 | r/w | parallel output port pins 63:32
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|=======================
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|=======================
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