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[/] [neorv32/] [trunk/] [docs/] [datasheet/] [soc_gptmr.adoc] - Diff between revs 69 and 73
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|=======================
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|=======================
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| Hardware source file(s): | neorv32_gptmr.vhd |
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| Hardware source file(s): | neorv32_gptmr.vhd |
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| Software driver file(s): | neorv32_gptmr.c |
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| Software driver file(s): | neorv32_gptmr.c |
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| | neorv32_gptmr.h |
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| | neorv32_gptmr.h |
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| Top entity port: | none |
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| Top entity port: | none |
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| Configuration generics: | _IO_GPTMR_EN_ | implement timer when _true_
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| Configuration generics: | _IO_GPTMR_EN_ | implement general purpose timer when _true_
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| CPU interrupts: | fast IRQ channel 12 | transmission done interrupt (see <<_processor_interrupts>>)
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| CPU interrupts: | fast IRQ channel 12 | transmission done interrupt (see <<_processor_interrupts>>)
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|=======================
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|=======================
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**Theory of Operation**
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**Theory of Operation**
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**Timer Interrupt**
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**Timer Interrupt**
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The timer interrupt is triggered when the timer is enabled and `COUNT` matches `THRES`. The interrupt
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The timer interrupt is triggered when the timer is enabled and `COUNT` matches `THRES`. The interrupt
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remains pending until explicitly cleared by writing the according `mip` CSR bit.
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remains pending until explicitly cleared by writing zero to the according <<_mip>> CSR bit.
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.GPTMR register map (`struct NEORV32_GPTMR`)
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.GPTMR register map (`struct NEORV32_GPTMR`)
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[cols="<2,<2,<4,^1,<7"]
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[cols="<2,<2,<4,^1,<7"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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