| Line 44... |
Line 44... |
writing zero to it.
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writing zero to it.
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**Timer Interrupt**
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**Timer Interrupt**
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The timer interrupt gets pending when the timer is enabled and `COUNT` matches `THRES`. The interrupt
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The timer interrupt is triggered when the timer is enabled and `COUNT` matches `THRES`. The interrupt
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request is indicated via the _GPTMR_CTRL_ALARM_ control register bit. This bit as well as the actual
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remains pending until explicitly cleared by writing the according `mip` CSR bit.
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interrupt keeps pending until the bit is explicitly cleared by application software or if the
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timer is disabled.
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.GPTMR register map (`struct NEORV32_GPTMR`)
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.GPTMR register map (`struct NEORV32_GPTMR`)
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[cols="<2,<2,<4,^1,<7"]
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[cols="<2,<2,<4,^1,<7"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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|=======================
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.6+<| `0xffffff60` .6+<| `NEORV32_GPTMR.CTRL` <|`0` _GPTMR_CTRL_EN_ ^| r/w <| Timer enable flag
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.5+<| `0xffffff60` .5+<| `NEORV32_GPTMR.CTRL` <|`0` _GPTMR_CTRL_EN_ ^| r/w <| Timer enable flag
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<|`1` _GPTMR_CTRL_PRSC0_ ^| r/w .3+| 3-bit clock prescaler select
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<|`1` _GPTMR_CTRL_PRSC0_ ^| r/w .3+| 3-bit clock prescaler select
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<|`2` _GPTMR_CTRL_PRSC1_ ^| r/w
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<|`2` _GPTMR_CTRL_PRSC1_ ^| r/w
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<|`3` _GPTMR_CTRL_PRSC2_ ^| r/w
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<|`3` _GPTMR_CTRL_PRSC2_ ^| r/w
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<|`4` _GPTMR_CTRL_MODE_ ^| r/w <| Counter mode: `0`=single-shot, `1`=continuous
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<|`4` _GPTMR_CTRL_MODE_ ^| r/w <| Counter mode: `0`=single-shot, `1`=continuous
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<|`5` _GPTMR_CTRL_ALARM_ ^| r/c <| Pending interrupt/alarm, cleared by setting bit to zero
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| `0xffffff64` | `NEORV32_GPTMR.THRES` |`31:0` | r/w | Threshold value register
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| `0xffffff64` | `NEORV32_GPTMR.THRES` |`31:0` | r/w | Threshold value register
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| `0xffffff68` | `NEORV32_GPTMR.COUNT` |`31:0` | r/w | Counter register
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| `0xffffff68` | `NEORV32_GPTMR.COUNT` |`31:0` | r/w | Counter register
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|=======================
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|=======================
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