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[/] [neorv32/] [trunk/] [docs/] [datasheet/] [soc_icache.adoc] - Diff between revs 60 and 61
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Rev 61 |
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| | _ICACHE_BLOCK_SIZE_ | size of a cache block in bytes
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| | _ICACHE_BLOCK_SIZE_ | size of a cache block in bytes
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| | _ICACHE_ASSOCIATIVITY_ | associativity / number of sets
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| | _ICACHE_ASSOCIATIVITY_ | associativity / number of sets
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| CPU interrupts: | none |
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| CPU interrupts: | none |
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|=======================
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|=======================
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[NOTE]
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The default `neorv32_icache.vhd` HDL source file provides a _generic_ memory design that infers embedded
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memory. You might need to replace/modify the source file in order to use platform-specific features
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(like advanced memory resources) or to improve technology mapping and/or timing.
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The processor features an optional cache for instructions to compensate memories with high latency. The
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The processor features an optional cache for instructions to compensate memories with high latency. The
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cache is directly connected to the CPU's instruction fetch interface and provides a full-transparent buffering
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cache is directly connected to the CPU's instruction fetch interface and provides a full-transparent buffering
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of instruction fetch accesses to the entire 4GB address space.
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of instruction fetch accesses to the entire 4GB address space.
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[IMPORTANT]
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[IMPORTANT]
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